Delay slot

In computer architecture, a branch delay instruction is a machine instruction that directly follows a conditional branch instruction, regardless of whether the branch was taken or not, is always running. The position of such a machine instruction in the pipeline is called branch delay slot ( waiting area ). Branch delay slots are used to make better use of the pipeline. They can be found both in various RISC architectures such as MIPS, PA-RISC and SPARC as well as in DSP architectures as μPD77230 and TMS320C3x/TMS320C4x.

Operation

For processors that use a pipeline, the execution of an instruction is divided into several stages. A plurality of instructions are executed in parallel, wherein in each step just one command is executed.

For branch instructions, there arises a so-called hazard: if the next instruction is loaded, the branch instruction is not executed yet finished; therefore it is not clear which command is to be loaded. Therefore, must be serviced by a branch instruction. To take advantage of this waiting period, the branch delay instruction is used. It is performed in any case, regardless of the result of the branch instruction.

• Computer Architecture