Emitter-coupled logic

Emitter coupled logic (English emitter coupled logic ECL ) denotes electrical circuits for logic gates in digital technology. As an active component is used in these circuits is used as the transistor-transistor logic of the bipolar transistor. However, the ECL technique is much faster, i.e., it has shorter gate delay times. A disadvantage is the high power dissipation. These properties brought this logic to a jocular saying: " ECL - hot and fast ."

Construction

ECL gates are typically operated with negative operating voltage. The base element of an ECL circuit is a differential amplifier. A plurality of transistors are connected to the emitter terminal of each other and guided via a common constant current source. The figure shows the differential amplifier from the input transistors Ve1 and Ve2 and the transistor V1 is formed. The number of transistors for the inputs is circuit -dependent and can be extended if necessary. A constant voltage ( U ref ) is applied - on the basis of V1 is a voltage divider - consisting of the resistors R3 and R4. If the input voltages Vi1 and Vi2 have a low level, the transistors Ve1 and Ve2. Thus, the emitter current flows through the transistor V1 and thus causes a voltage drop across the resistor R2, whereby the transistor Va1 is triggered. Characterized Vo1 goes to the low level and Vo2 to the high level. Thus, in positive logic is the output with Ua1 the output of an OR operation and the output Vo2 with the output of a NOR operation.

The gain difference per stage is in the customary digital circuits, a range of 30 times, and is limited by the amount of operating voltage. This can result in slow input edges, since the logic is always in the linear region, the parasitic oscillations occur. There are but also high-frequency amplifier, oscillators (> 1 GHz), line receivers, and comparator circuits with extreme data rates possible.

The ECL family is among the fastest available logic families. This is achieved because (in contrast to, for example, in transistor-transistor logic) in the normal operating state is not a transistor in saturation. ECL circuits with delay times of <200 ps, can be achieved, which ECL circuits are faster than the Schottky -TTL - circuits, which also do not go into saturation. The difference is due to the fact that the collector-emitter voltage across the transistors conductive > 0.6 V is higher, which results in not only a larger distance to saturation, but also a reduction in the collector-base junction capacitance. A further increase in speed is due to the small signal amplitudes during switching of only 0.8 V. Thus, the junction capacitances are reloaded quickly. The low output impedance of the emitter follower ra also accelerated the speed. The output resistance is obtained from the context of the collector circuit:

Moreover, an almost constant current flows through the circuit. It no large current spikes as with other logic families.

Compared with other logic circuits, the power consumption is very large when the gate does not switch. However, at high frequencies the power consumption is lower, since the power consumption of CMOS logic, for example, increase linearly with the frequency, but remains nearly constant of ECL logic. But CMOS has the advantage that it can be integrated cheap and can realize the progressive miniaturization easier.

Dimensioning

In the event that the transistor V1 closes, a voltage drop of about 0.2 V occurs across the resistor R2, which is caused by the current at the base via transistor Va1. For the voltage Vo2 at the emitter of transistor Va2 obtained through the equations of the differential amplifier, an electric potential of about 0.9 V, which is the high level. If this high level is applied to one of the inputs, the result for the electric potential UE:

Thus, the transistors do not come into saturation at the entrance, shall not come under 0.6V, the collector -emitter voltage. It follows the minimum collector potential:

Therefore, the low level is chosen with 1.7V. Now, the reference voltage Uref must be selected so that the input transistors are conductive at a high input voltage of -0.9 V and terminate at a low input voltage of -1.7V. This is achieved by placing a value Uref exactly between these values ​​:

The maximum allowable input low level of ULow, max = -1.5 V has the NOR output bear a high level of at least Ua2 = 1.0V. At the lowest allowable input high level of UHigh, min = -1.1 V may have the low level at the output a maximum of 1.6V.

In contrast to the other logic families, the input voltage in the high- pass upward is very limited and may not exceed 0.8 V, so that the input transistor is not saturated. In the transfer characteristic to this becomes apparent as a bend at about -0.4 V at the NOR output. Upon further voltage increase at the input due to the saturation of the input transistor is lowered, the potential at the collector and emitter (UC and UE), whereby the voltage Vo2 at the output rises.

Of the characteristic curve it can be seen that the logic level at the zero potential closer than at the negative supply voltage. In addition, the size of the operating voltage for the logic level is not relevant as it is defined only by the base-emitter voltage of the emitter follower. Would be set to a negative level as a reference potential, it would overlap the level, which would not allow the reliable operation due to the low level.

The power loss of a single gate type MC10xxx is 25 mW. In addition, there occurs a loss of power to the emitter resistors, which again makes per 30 mW with an average output voltage of -1.3 V and 510 Ω. This is more than consumed the entire gate. Emitter resistors are therefore connected only at gates used, which is why they are not housed in the IC package. The power loss across the emitter resistors can be reduced to about 10 mW, when the operating voltage is reduced to 2V, and the resistors 50 Ω are large. However, the voltage in the power supply efficiency (i.e., high efficiency ) has to be generated, otherwise shifting the only power dissipation of the circuit into the supply. The -2 V are therefore not generated by a linear regulator from 5.2V. However, the additional effort required in the supply is only useful for many ECL gates.

Wired -OR

The parallel connection of ECL outputs can be due to the open- emitter outputs, comparable to the wired-AND with open-collector outputs to achieve a TTL circuit, a logical OR operation. The advantage of this combination is that it saves next to or on the basis of the savings of the gate power dissipation and latency.

The structure of the circuit is shown in the adjacent figure. By wiring the OR and NOR outputs results in the context:

Application

Due to their high power ECL gates are not suitable for VLSI circuits, so extremely high integration. However, they are used specifically where requiring extremely short switching times and / or constant power consumption with frequent gate changes, say for example in a particularly fast ALU of a microprocessor. However, the ECL technology is being replaced in some areas increasingly to ever increasing CMOS technology.

Another field of application for ECL technology are bus drivers for extremely fast differential signal transmission (see Balanced signal transmission and LVDS).