Glitch

In electronics, we denote by Glitch [ glɪtʃ ] a momentary false statement in logic circuits and temporary corruption of a Boolean function. This occurs because the signal propagation times in the individual gates are never completely equal. This falsification is therefore also called race condition. Susceptibility to glitches increases with the complexity of the speed increase and reduction of circuits, but can also be present in very simple circuits. They are a major problem in the development of modern electronic circuits and microprocessors faster dar.

A glitch is sometimes referred to as hazard (English: "danger, risk, chance " ): means ( " peak, thorn " engl.) or Spike.

• 5.1 D flip- flops
• 5.2 Approximation of delay times
• 5.3 Systematic approach

Example

It is given a circuit which has three inputs x1, x2 and x3. You should return the value " 1" if at least one of two conditions is met:

• X1 and X2 are the same "1" or
• X1 is equal to " 0" and x3 "1" simultaneously

Does not apply at least one of the two conditions, it should output "0".

The circuit located now in situation 1 According to our specifications is the first condition is satisfied, namely x1 and x2 are "1". The branches that carry the information "1" are displayed in red. The inverter converts the incoming "1" to a " 0". Therefore, the following AND gate does not transmit a signal, there is a " 0". But the overall circuit ( OR gate ) yet provides a "1" because the other AND gate, the "1 " signal.

In Situation 2 is x1 = 0 and x3 = 1. The circuit is still a "1" output. However, the inverter requires a certain time to go from " 0" to a "1" to perceive the transformation of x1 signal. For a short time is both x1 = 0, and (x1) ' = 0 This condition is processed as if none of the conditions is satisfied, and is thus a " 0". This situation is referred to as a glitch.

After some time - on the order of nanoseconds - the circuit is in Situation 3: The inverter has processed the new information. The now "1" output goes to AND gate which ( after a short delay ) then a "1 " signal. The complete circuit now supplies the desired "1".

Distinctions

Functional and structural glitches

Function hazards caused by the simultaneous occupancy change of more than one variable. These hazards can be avoided by appropriate assignment change ( Gray coding ), by timing or by a delay ( RC network at the output ).

Structural hazards arise in circuits with more than one stage by the change of a block in the KV diagram ( = gate in the circuit ) in an adjacent block ( no overlapping blocks in the KV diagram). These hazards can be avoided by the implementation of redundant Primkonjunktionen ( overlapping blocks in the KV diagram) or by pulsing.

Under this nomenclature is in the example given above is a structure hazard.

Static and dynamic Glitches

There are two types of glitches: static and dynamic. Static is a glitch if there is no change in the output value is to take place, but the glitch briefly provides the other value. A dynamic glitch, however, once again jumps after a change to the new value just on the old back.

Depending on whether the glitch occurs in the change to a 1 or a 0, is still 0 or 1 glitches glitches different.

Importance of glitches

In practice, time differences also exist in the gates of the same type or different in the long lines. If you want to know the exact value of the function, one must have an appropriate time to wait until all the glitches are eliminated. This fact substantially limits the clock rate of modern processors.

Elimination

An important tool for the design of switching functions are the Karnaugh diagrams. In principle, it is possible to realize larger circuits without glitches. However, one needs to other components in the circuit and even at more complex structures whose number is enormously large, which increases the cost of the circuit. It is important to find a good compromise between the cost of the circuit and the duration of the glitches.

Avoid the impact

D flip- flops

The effects of glitches can be prevented in synchronous circuit designs by downstream D flip-flops. The idea is that the outputs of the combinational circuit parts, consisting of several gates of different maturity, only then must accept valid states when the clock edge assumes the output values ​​to the D flip-flops. In the time between two clock edges as many glitches can occur in the combinational part by transit time effects, since these intermediate states are not observed by the downstream D flip-flop. The downside is that as the smallest unit of time the clock period of the D flip-flop occurs and no time- continuous output signal as in a purely combinational circuit is no longer present.

The method, which always provide outputs of combinational circuit parts with D flip-flops, is one of the essential foundations for stable, digital circuit design in complex, user-programmable FPGAs.

Approximation of the delay times

In the above example, this procedure would be to add another ( nonfunctional ) gates in the upper branch of the outgoing line of the input x1, so that the change in signal reaches the two AND gates simultaneously. This method is, however, fraught with some uncertainty and does not provide secure the desired result.

Systematic approach

The better method is the systematic approach. To do optimizes the relevant circuit underlying KV diagram. Which belongs to the above example diagram shows two blocks which are realized by the two AND gates ( disjunctive normal form ). The hazard arises during the transition between these two blocks. Resolves the hazard, if you bypassed this transition with another, logically the superfluous, block that overlaps with two blocks: x0 and x2 are both "1". In the resultant circuit, a further AND gate must then be inserted accordingly. The circuit can then statically but not be fully tested because a faulty AND gate does not really stand. The hazard can be measured technically not included in today's gate delays.

Note, however, that not only different periods may affect individual gates in the form of glitches, but also the different long running times of the signals in the connecting lines. The individual connection lines must be modeled using the transmission line theory. These terms are not observed in the systematic resolution using Karnaugh maps. Therefore, this method can only be used at relatively low switching frequencies ( = the case of quasi-stationary ) or discrete circuit elements, which are operated with a correspondingly adapted connection lines. At high signal rates, with 100 MHz can be used as a rough guide and if the concrete routing (for example, the case of interconnection within FPGAs) by the developer only a small influence can be taken, also supply resolved combinational circuits not glitch - free designs.