Half adder

A half-adder (English half adder ) is a switching network, commonly implemented as a digital circuit. It consists of two inputs and two outputs. With a half-adder can add two single-digit binary numbers. Here, the output provides s (English sum - " sum " ) the right and the output c ( carry - "carry " ), the left digit of the result.

The following truth table shows the operation of a half adder:

Corresponding to the equations

And

This refers to the symbol or in the literature also common the XOR operation ( "exclusive or "). The XOR operation is, therefore, also colloquially referred to as the carry -free addition.

The figure below shows the structure of a half-adder using only AND and OR gates. The required XOR operation is thereby converted by a combination of two AND gates with an OR gate. In the figure above, a simpler implementation is shown in which an XOR gate is used for the output s.

Half adders are frequently part of microprocessors. Likewise, this logic function can be implemented as part of an overall circuit in a programmable logic device (PLD ), a FPGA or an ASIC. With discrete logic components, this circuit function is hardly realized today, because with these components, the required high clock frequencies usually can not be achieved and the circuit complexity of the installation and the cabling is much too large.

From two half-adders and an additional OR gate a full adder can be built.

The half adder is used in combination with full-adders for constructing Addiernetzen.