Interrupt

In computer science is meant by interrupt ( engl. to interrupt, interrupt ) the short-term interruption of normal program execution to perform a different, usually short, but time-critical processing.

The triggering event is called interrupt request interrupt request ( IRQ). Thereafter, the interruption routine (interrupt service routine ISR) is executed. Then, the execution of the program at the point of interruption continues.

Interrupts can for example be sent from input and output devices as soon as they have completed a task. For this purpose, a signal is placed on the bus or directly to a dedicated processor pin ( IRQ input ), which was specially allocated for it.

Older computer models had no interrupts. In the 1960s there were the first models with interrupts, an example was the Electro Logica X1.

Interrupts are triggered by asynchronous external events. Asynchronous signifies in this context, that the current program is not always stopped at the same point.

Purpose

Sense of an interrupt to (eg keyboard, mouse, hard disk, network, timer / timer, etc. ) can react immediately to Ein-/Ausgabe-Ereignisse (signals ), while another program code (eg is processed by application programs ). From the interface hardware only an interrupt is triggered and is only required if the next operation on the interface (hardware ) is not possible, for example when buffer is empty ( output ) buffer full ( input ), error messages of the interface hardware or an event even without data transfer (eg timer).

In addition, there are only interrupts the technique of programmed ( cyclic ) polling (polling ) to know the status of input and output devices, processes, etc.. Although this method is simple and does not require any additional hardware, but is much less efficient than working with interrupts, since CPU power is constantly occupied. In multitasking operating systems, the polling is not possible as the sole method.

The standard analogy for interrupts in daily life is a door bell: While you do its thing, you can be interrupted at any time by the bell when a guest a " completion" of desires, and then turn to him. When polling - that is, without bell - would have to be constantly running to the door to see if attendance is there or not. When heating milk on the other hand, it is probably better not to wait on the " Interrupt" of overcooking, but rather to monitor the progress regularly.

An example of an application of interrupts can be displayed in a processor after it has issued an order to a hardware component does not have to actively wait for an answer (polling), but in the meantime can do other tasks to later using an interrupt to be retrieved by those hardware component back to this Ein-/Ausgabeaktion. Without interrupts, for example, would also be pre-emptive ( = displace by running applications ) multi-tasking operating systems not possible, since otherwise programs no longer interrupted by the operating system switched ( timeshare ) and input and output devices could no longer be operated.

Expiration

Are triggered external interrupts ( hardware interrupts ) by means of a so-called interrupt request ( IRQ =, " interrupt request "), a signaling to the interrupt signal input of the CPU. There are a plurality of interrupt sources, an interrupt controller between these signal inputs and the processor is connected to the administration times. When an interrupt request from the CPU, it is assumed ( by the end of a current instruction, and if not disabled the interrupt ( "masked" ) is ) through a fixed sequence of the interrupt cycle decreases. In the interrupt cycle the CPU of the old (broken ) command counter status is also backed the status register on the stack ( Intel code segment and instruction pointer ) and in some architectures. Now the triggering source of the interrupt request must be determined. In most CPUs, the source is identified within the interrupt cycle has a value on the data bus, which is usually set by the interrupt controller, thus found, the corresponding interrupt vector and triggered the jump to the appropriate interrupt service routine ( ISR). Before or during the ISR nor the edited IRQ must be deleted so that it will not be triggered again. Intel ( = PC) compatible architecture this is done by the I / O instructions within the ISR. (So ​​might be able without special measures in software because of the ( short ) duration will be up to the erasing instruction also 'real' IRQ deleted. ) For some CPU architectures, especially in microcontrollers, there can be multiple interrupt inputs, which here the interrupt controller is already integrated. In simple CPUs only the IRQ and interrupt cycle occurs, which must be checked by software which source was the cause and which accordingly is routine work off.

Standing up to the time of the interrupt cycle several IRQs of several resources, it is determined by a selection process by the hardware ( interrupt controller ) is the vector of the main interrupt request and processed ( usually by priority method, less often by random method, but not for an order). Following the processing of other pending IRQs follows.

Hardware- triggered ( external ) interrupts are maskable total by a special instruction, that is, the assumption can be prevented by software ( masked) or enabled again. (This can for example be necessary in device drivers for some time-critical and synchronized routines. ) Most CPU architectures (power failure, memory failure, etc.) are for special cases also implements non- maskable interrupt ( non -maskable I. = NMI) always trigger a jump of the processor in the interrupt routine. Without special measures, these NMIs can also interrupt their own service routine (ISR ), which can lead to significant software problems. So that this does not happen with normal ( maskable ) interrupt requests, the interrupt masks the interrupt logic in the CPU during normal interrupt cycle before jumping to the ISR automatically. After execution of the ISR is the return to the interrupted program always restore the old state ( through restitution of the status register ).

External interrupts are compared to the interrupted program asynchronously in principle, ie they occur at an unspecified date. Therefore, interrupts may not hold (eg hard disk) without special synchronizing measures not directly affect programs (or program variables), or to devices. ISRs are no tasks in the sense of the operating system. For ISRs should further be noted that lifted only with special software concepts within the ISR, interrupts (interrupt enable) must be, as both a Interruptschachtelung by foreign ISRs as well as a re-entry option ( Reentrance ) of the same interrupt is created.

Some processors have special commands to trigger so-called soft " interrupts " from an ongoing task applies except in the specific inputs and return conditions are like subroutine calls and therefore are not asynchronous. The same goes for traps from the CPU to errors ( protected access, banned instructions ( eg division by zero), single step debugging, memory management events, but also as a standard interface to operating system calls, etc.) be self- triggered and usefully use the same mechanism.

Especially with hardware-based event-driven applications, as are common in embedded systems, for example, may execution of the system is practically in the interrupt routines (or in triggered by these tasks) laid. The processor is put into a power-saving sleep mode ( Idle State ), from which he ( ie with external events ) wakes up at interrupt requests - the real, main program 'consists then in the extreme case of only one initialization part, which is run after the system starts, followed by an infinite loop in which (apart from the activation of the above-mentioned sleep state ) nothing happens.

Basic sequence at the occurrence of an interrupt request (transition from hardware to software):

Categorization of interrupts

A distinction is made between precise interrupts and imprecise interrupts. Precise interrupts keep the machine in a well-defined state, not imprecise.

A software interrupt is nothing more than a program built into the software command, which acts as a hardware interrupt, it is called an explicit interrupt job. A hardware interrupt is directed against it from outside via a duct or the IRQ pin of the processor.

Another way to categorize interrupts, differs according to the timer:

• The input and output devices can send a signal that they are done with their job or had an error.
• The program can be triggered by arithmetic overflow, the divide by zero, attempt to perform an unauthorized machine code, or a reference to a destination outside of the allowed range an interrupt. This strikes a processor internal error detection and enables the interrupt on internal processor, but purely hardware-based signaling pathways.
• The timer allows the operating system to perform tasks on a regular basis. These ongoing programs are discontinued. For example, a timer can be either built into the processor as present as external module, in both cases seems to be running off like a Ein-/Ausgabeereignis.

Processor interrupts are also referred to as exceptions, and can be divided into three types:

• Abortion are very important errors, such as hardware failure,
• Errors ( faults ) occur prior to the completion of an instruction
• Traps occur after a statement on (insert when debugging ).

Hardware instance x86 architecture

All Intel processors have interrupt signal input for maskable interrupts. To use multiple interrupt sources to connect, there is a separate interrupt controller chip (eg the Programmable Interrupt Controller PIC) having a plurality of interrupt inputs and merges into one signal. He is also configurable via internal registers, so he ever different, predetermined interrupt vectors acting in accordance triggered interrupt in the CPU interrupt cycle on the bus, which then reads the CPU. With newer processors all these functionalities are integrated with the core of the main processor.

For x86 processors 256 different interrupt vectors are possible. The interrupt vector is read as 8- bit value from the data bus in the interrupt cycle of the processor. In x86 processors, the vectors themselves are not the indirect entry points. The vector will, in the REAL mode multiplied by 4 (binary shifting ) so that for each vector 32 -bit jump address can be accommodated, which is then bound. In protected mode is multiplied by 8, because a Descriptoreintrag is 8 bytes long. In real mode, the interrupt table is in the first kilobytes of main memory ( 0000h: 0000h - 0000h: 03FFh ). Each interrupt number requires 4 bytes: 2 bytes for the code segment and 2 for the offset within the segment. In protected mode, the CPU, the position of the table is set by the interrupt descriptor table. Here are needed for each interrupt 8 bytes for the descriptor entry in the ISR.