Latchup
The technical term latch -up effect (from English " snap ", also single event latchup SEL ) refers to electronic transition of a semiconductor device, such as in a CMOS level, in a low state, which can lead to an electrical short circuit. If protective measures are missing, the latch-up effect leads to thermal destruction of the component.
Can be triggered latch- up effect by a short electrical voltage spike, for example by over-voltage or electrostatic discharge. In addition, can also be alpha or neutron radiation cause a latch-up effect. Because of the ( much higher ) particle radiation in space is therefore not possible for the space use of some highly miniaturized components.
- 2.1 Structural countermeasures in the semiconductor
- 2.2 Countermeasures in the surrounding circuit
Cause
By the layer structure of each of doping n-and p -channel field effect transistors in a common substrate in an integrated circuit to undesired parasitic npn and pnp bipolar transistors result. These correspond in their mutual interconnection of a thyristor, as shown in the adjacent diagram using the example of an inverter in CMOS technology. The latch -up effect refers to the ignition ( turning on ) of this parasitic thyristor. Wherein the supply voltage is short-circuited in the component. The flowing current is then high enough to produce a thermal overload in this area and damaging the circuit or destroy.
Technical Description
The critical geometric structure composed of a parasitic lateral NPN and vertical PNP transistor. The source - drain regions of the p-channel transistor, the emitter and the n-well, the base of the PNP transistor thus formed, while the p-type substrate is the collector. The emitter, base and collector of the npn bipolar transistor formed in accordance with the source - drain regions of the n-channel field effect transistors, the p-type substrate and the n-well.
Both bipolar transistors are blocked under normal operating conditions. But flow due to external conditions, high lateral currents by bath and substrate ( for example, by overvoltage at one of the inputs of a CMOS circuit, the over - not shown here - are derived protection diodes in the substrate ), it is at these points to voltage drops. These voltages the polarity of the base-emitter diode of the two parasitic transistors in the forward direction. It comes at a flow of current. The resulting collector current produces a voltage drop in the base parallel resistance (Rp or Rn ) of the resulting complementary transistor. Is the base-emitter voltage is exceeded, also in this, then both transistors are conducting. The consequences are a positive feedback between the two parasitic bipolar transistors as well as a permanent low-resistance connection between the supply voltage and ground. This low impedance connection can be disconnected only by removing the power supply voltage.
Is the current gain of the two transistors is high enough, the arrangement remains even after the disappearance of the injected currents in the active state ( holding or latch-up condition). This leads to a malfunction of the component, because the outputs are at a fixed level and no longer respond to changes in input. The flowing current is also determined only by the resistance track and the resistance of the base-collector junctions of the transistors involved. The afferent metal tracks are not designed as a rule, and it can lead to thermal destruction of or merger with underlying structures.
Trigger mechanisms
- The supply voltage exceeds the absolute maximum ratings ( engl. absolute maximum ratings) of the block. A brief voltage spike as in an electrostatic discharge may suffice here.
- The voltage at the input or output terminal exceeds the supply voltage by more than the voltage drop of a diode. This can happen due to transients of a signal line, for example, due to crosstalk.
- Incorrect or insufficient sequence, are turned on in the different supply voltages in a circuit ( engl. power up sequencing). Yet unprovided circuit parts to which however already applied signals from already supplied circuit parts, so can go into the latch-up condition.
- Under normal circumstances a more uncommon cause of ionizing radiation such as alpha or neutron radiation. The latch-up effect results in unprotected operation of CMOS circuitry in the vicinity of (strong) radioactive sources to failure of the electronics. Also in this case, a single event be sufficient.
Countermeasures
Structural countermeasures in the semiconductor
In order to effectively suppress the triggering mechanisms described above, the following measures may be taken:
- Large distances of the source drain regions to the well edges
- Low-resistance substrate and the p -type guard ring (English guard ring ) adjacent to the n -well
- Low-resistance n -type guard ring for the supply voltage terminal
- Isolation of the individual FETs by SOI substrates
In this case, the following problems arise. In a highly doped material ( low electrical resistance), no low- well regions can be implanted. Therefore, we used epitaxially coated wafer carrying a thin high-impedance ( low doped ) silicon layer on the highly doped material. The epi-layer absorbs tubs and transistor regions and the underlying conductive substrate well then provides an effective latch-up protection. The only disadvantage of this method is the high cost due to the additional coating process.
Other measures are more structural nature and relate to short connections of cables with high currents and the already mentioned in the enumeration of guard ring structures. These guard rings are highly doped p -type structures in the p-type substrate and the n -doped patterns in the n-well. You will earn on injected carrier and they withdraw the Lateralstrom. Guard rings can only be realized very space consuming, but are used for critical input and output circuits in CMOS technology.
CMOS circuits have advanced in order to suppress this interference effect on the inputs on particular geometric arrangements of the doping regions of the n and p- FETs. In aerospace, protective circuits (fast current limiter ) can be used. Another caused by space radiation disturbance, called the SEU ( Single Event Upset ), does not lead to destruction of the circuit but only on a temporary lowing disorder - depending on the circuit also up to block, but this can be remedied by switching. Both effects, SEL and SEU are also referred to as single event effects, since they can be triggered by a single high-energy particles.
Countermeasures in the surrounding circuit
It is also possible countermeasures outside the semiconductor device are made. Generally, these are measures that ensure that the absolute maximum ratings of the module are not violated:
- Maintaining an A for connection and disconnection of the operating voltages coupled together components ( power sequencing ), so that no undue stress differences between component connections occur.
- Wherein two power supply voltages for the device can ensure a Schottky diode between the supply that these differ only by the voltage drop of the diode.
- Inputs, external protective resistors are connected upstream to prevent the input current reaches the value of a latch-up
- Protect the components and component connections from transients (caused by ESD or switching operations ) with varistors or suppression diodes
- Current limitation of the supply (through a series resistor ). While this does not prevent the latch-up, but prevents the thermal damage to the component.
Disadvantage of these measures is that additional components result in higher costs. Even the limited space on a printed circuit board can have a limiting effect on the use of these measures.