PCI Express

PCI Express ( " Peripheral Component Interconnect Express ", abbreviated as PCIe or PCI - E) is an extension of standard for connecting peripheral devices to the chipset of a main processor. PCIe is the successor to PCI, PCI -X and AGP and offers in comparison to its predecessors, a higher data transfer rate per pin.

During their development, the interface " 3GIO " was called, which stands for "3rd generation Input / Output".

• 3.1 Pin Assignment

Technology

PCI is compared with the parallel PCI bus is not shared ( shared) bus system, but is a separate serial point-to -point connection. Individual components are connected via switches. These make it possible to establish direct links between individual PCIe devices, such that the communication of individual devices does not affect each other, the achievable data rate of other devices.

In PCIe there is no separate clock signal, only a much lower reference clock is transmitted separately. Clock recovery is carried out from the received signal. This is therefor specially coded (up to PCIe after 8b/10b from PCIe 3.0 a " scrambling " encoding which two synchronization bits each 128 net data bits prefixing ).

For sending the data are parallel-to -serial converter, and to receive serial-to- parallel converters used in the assemblies. Despite this very different physical structure PCIe is fully software- compatible with PCI, so that neither operating systems and drivers nor application programs need to be adjusted.

PCIe is full duplex and operates according to the version with 250, 500 or 984.615 MB / s per lane and direction. Version 4.0 will allow 2000 MB / s.

All data transfers and all the signals (e.g., IRQ ) to the PCIe link are divided into packets. Due to the fundamentally different electrical structure and the other form of transmission no mixing devices are possible, which could be operated in both PCI and PCIe slots. This is enforced by changing connections, so that must be used for the use of PCIe cards according to newer motherboard or controller.

PCIe PCI principle is as hot -pluggable, which allows the installation and removal of (eg defective ) expansion cards during operation, provided that the hardware and the operating system support.

Transfer layers

The transfer is represented by several layers, each of which communicates only with the directly adjacent layers, as well as performing for the data transmitted on this layer data error detection or correction.

The lowest layer, the so-called physical layer provides the electrical connection between two directly connected devices Represents the include a device (eg a plug-in ) and the nearest switch. The logical connection ( " link" ) between these devices is composed of one or more lanes. Each lane in turn consists of two line pairs, a respective differential pair for the sending and receiving.

All data that is transferred between PCIe devices are mixed transmitted over these lines, in contrast to PCI so there are no own lines more for the signaling of interrupts. However, since the serial protocol can not be stopped, there is a slightly higher and fluctuating interrupt latency than with classic PCI with dedicated interrupt lines.

The data link layer transmits the data packets of the Transaction layer between the two link partners. For this purpose, it provides them with a sequence number and a 32 -bit CRC value, the link CRC ( LCRC ) as above. Received packets are communicated to the direct link partner using Data Link Layer Packets, as well as the condition of the package. Damaged or lost packets are sent by the partner again. Thus, the higher layers are decoupled from electrical transmission interference.

The Transaction Layer transported ultimately the user data between the logical sender and receiver, ie excluding the intervening switches. The Transaction Layer Packets (TLP) in the header a label to what it is for a type of transmission. Typical examples are write accesses ( writes ) and read requests ( reads) and read responses ( Completions ). Write accesses are posted called transactions, that is, they are sent and produce on the Transaction Layer no answer.

Quality of Service

PCIe as a new feature compared with PCI " Quality of Service". These virtual channels " Virtual Channels " (VC ) are used, where a priority, " Traffic Class" (TC ) is assigned. The default is for the traffic over VC0 with TC0. By the use of different virtual channels of specific data traffic to be prioritized.

A typical application would be a sound card when recording: Can they send their data will not be in time about the connection because the connection is otherwise occupied, running sooner or later the buffer on the sound card and data is lost. For this real-time application would prioritize traffic.

Power supply

A PCI Express slot can supply the device connected to it with power. According to the specification, the power supplied for an ordinary slot of PCI maximum of 25 watts for low -profile cards shall not exceed 10 watts and at a PEG ( PCIe x16 ) slot maximum of 75 watts. Since, however, is not enough for some applications such as video cards, the specification allows for different additional plug for power supply before, so-called PCI Express ( Graphics) Power Supply Connector ( also PEG connector or PCIe cable ) that provide 12 volts.

The first version of the auxiliary connector has six pins and can supply up to 75 watts, making the device the maximum supplied power increases to 150 watts, when using two such connectors even at 225 watts. In the specification of PCI Express 2.0, a new feature connector with 8 pins was defined, which can result in a maximum of 150 watts. For even higher performance, an additional connector with 6 pins can be used, but this leads only another 75 watts, whereby the maximum input power of a PCI Express card is limited to 300 watts ( 75 watts from the socket, 150 watts first plug, 75 Watt second plug). New powerful graphics cards that are on the market since early 2011, provide for the use of two 8 -pin connectors. Thus, the maximum power consumption increases to 375 watts. (75 watts from the socket, 150 watts first plug, 150 watt second plug). This last extension is not yet official, but is already being used in such products.

Slot sizes

PCI Express card and PCI Express slots have two properties:

• The mechanical length of the slot: According to the length of the slots or slot of 25 mm, 39 mm, 56 mm or 89 mm is referred to as PCIe x1, PCIe x4, PCIe x8 or PCIe x16. In slots, there are still open slots, into which you can plug any mechanically cards.
• The maximum usable lanes of a slot or a PCI card: Often they meet the requirements of length, but can be smaller, but never larger. Frequently encountered are mechanical PCIe x16 slots that are electrically only PCIe x4 or x8 PCIe. In particular, it is often the case that motherboard with multiple PCIe x16 slots to provide this while using fewer lanes ( see below).

In the desktop area PCIe x1 is mostly used as a substitute for the PCI bus and PCIe x16 as a substitute for the AGP bus for connecting video cards. PCIe x4 are mainly found in the server area for cards with high throughput ( disk controller, 10GE ​​NICs ).

In the server and workstation area there is also still the PCIe x8 and x32 versions. The slots are also backwards compatible, which means a x1 card can be inserted, for example, in a x4 slot, only one lane is from the four lanes of the slot then used. Some motherboards have PCIe slots without a trailing ridge, so that " larger" cards can be plugged.

It is also possible that slots have a different design from the connection of the lanes. Often found which is about SLI and Crossfire. For although the slots are the size of x16 slots for graphics cards, the 16 lanes distributed when using two graphics cards on both slots, if the motherboard and respectively of the built chipset no 32 lanes for both graphics cards providing what then only eight lanes per card results. However, this down- clocking found not only in two graphics cards instead but also for example when using a x16 graphics card and a x1 card, so the graphics card only runs at PCIe x8.

The slot is mechanically divided into two sections: the left section always be 22 pins, which are mainly responsible for the power supply and clocking. On the right side are depending on the number of compounds 14-142 pins, which are designed for the actual data transmission.

Current motherboards with PCI Express support up to 68 lanes - usually divided into one to six x16 slots for the graphics card ( s) ( of which partially some are electrically operated with fewer lanes, see above ) or an x16 - and a x4 slot, plus several x1 slots and internal connection of other devices on the motherboard built-up (eg, gigabit network chips, so they do not have to be connected via the much slower PCI bus ).

In addition, there are notebooks miniaturized versions of PCIe, among other Mini PCI Express for WLAN or as SSD and the Mobile PCI Express Module for video cards.

Pin assignment

Top = component side, Bottom = Solder

Compatibility of slots and cards

The PCI standard requires that each card can connect both with a width of one lane and with the electrically assisted by the card Lane Number. For slots, the same applies. Other widths connection - the standard provides for 1x, 2x, 4x, 8x, 12x and 16x - and are optional. A compound having the maximum width is then the state is supported by both the slot and from the card.

Since the electrical width may be less than the design and some link widths are optional, it is not obvious how broadly a card in a given slot will work. The "PCI Express Label Specification and Usage Guidelines " of 2006, therefore, recommend, just to list on each slot and on each card, which connection widths are supported. However, this is rarely implemented.

Compatibility of slots and card PCIe versions

Notes: