Programmable logic array

A programmable logic array, often referred to in the English-language specialist literature as programmable logic array or PLA short, is a semiconductor circuit which consists of two series-connected AND - and OR matrices. A term rarely used is Field Programmable Logic Array ( FPGA ). A PLA is used to make switching networks and plants for logic functions in disjunctive form used. The AND - matrix represents the case of conjunction. The selection of the components of conjunction takes place in the context of programming ( usually by means of a special device ) by the removal of switching elements from the AND matrix. The disjunction of conjunction is effected by means of the OR matrix. The technical implementation of the two matrices is done, however, often means NAND gates.

Nowadays PLAs are rarely used and have been almost completely superseded by CPLDs. CPLDs as PLAs have no restrictions concerning the availability of UND-/ODER-Matrizen in the entrance area are electrically programmable and erasable and again, such as FPGAs are programmed in uniform hardware programming languages ​​such as VHDL and moreover include a certain number of registers.

Realization

Originally an array of fuses ( fuse engl. ) was used, with individual fuses were blown with a high current during programming to be programmed according to the bit pattern. One of the problems of this technology was that could over time, through crystallization processes, "fix" individual fuses.

The newer technology, the PLA antifuse consists of a diode array in which each diode representing one bit. In contrast to the Fuse technology, where a conductive connection is interrupted, here the diodes are connected such that they usually block the current. During the programming process target specific diodes are now burdened with a very high current. These diodes are destroyed thereby to form a conductive connection.

According to the " burning " of the PLA, the written data is represented by a bit pattern of defective functioning and diodes. These data can now be read as often (the " read current " course below which is which is used for programming ). PLAs belong to the group of OTP devices.

The number of inputs and outputs do not have to be identical. Once a programmed block can not be changed, which is not in the final series production annoying. During the development phase of electronic circuits like so-called GAL (Generic Array Logic ), however, are used, the delete several times and can reprogram.

Illustrative example

Input signal 1: Anschaltknopf ( on / off) Input signal 2: Safety switch ( on / off) Output: motor ( on / off) A possible programming would be:

If Anschaltknopf to AND safety switch = on =, then motor to =. If Anschaltknopf = on AND safety switch = off OR if Anschaltknopf = from AND to OR = safety switch if Anschaltknopf from AND safety switch = off =, then motor = off. The motor may also be controlled by two switches in series, so that the circuit is closed only when the Anschaltknopf and safety switches are closed. In the example, but the use of a PLA will be illustrated. In PLAs input and output signals can now be linked together in a complex manner in a confined space.

Demarcation and special cases

In colloquial usage, the term PLA or GAL for the area of the "smaller " building blocks of programmable logic has prevailed, while the terms ASIC, FPGA and CPLD have set depending on the type of implementation for components of "higher" complexity.

To special cases of PLAs is at the following programmable logic circuits:

• Programmable Array Logic (PAL): Only the AND array is programmable.
• Programmable Read - Only Memory (PROM ): Only the OR array is programmable.