Serial Peripheral Interface Bus

The Serial Peripheral Interface ( SPI) is a system developed by Motorola bus system with a " loose" standard for a synchronous serial data bus (Synchronous Serial Port ), with the digital circuits on the master- slave principle can be connected together.

A similar bus system under the name Microwire exists by National Semiconductor.

Basics

Properties

• Three common lines to which each subscriber is connected

• One or more active at logic 0 chip select lines, which are all driven by the master and slave of which each is provided per line. These lines are referred to variously depending on the application with names like SS, CS or STE for Slave Select, Chip Select or Slave Transmit Enable, often in combination with an index number to distinguish. There are also special applications where several slaves share a line, see Figure 1
• Full duplex capability
• Many settings, such as with which clock edge is output or input
• Word length
• Transmission: MSB or LSB first

Many options are required, among other reasons, because the specification is not defining for the SPI bus in many properties, so different, mutually incompatible devices exist. Frequently, for example, a separate configuration of the controlling microcontroller ( master of the SPI bus ) is required for each connected circuit.

Many microcontrollers, like most AVR, permit via the SPI bus in-system programming ( ISP also short ).

Protocol sequence and settings

It can be connected theoretically unlimited number of participants to the bus, however, it always just has to be a master, which in turn generates the clock signal SCK. The master sets with the line " Slave Select ", with which slave it wishes to communicate. If they pulled to ground, the respective slave is active and " listens" to MOSI, it stores its data in the clock of SCK to MISO. It is transferred a byte from the master to the slave and the other byte from the slave to the master.

A protocol for data transmission was not determined by Motorola, but have prevailed in practice four different "modes". These are determined by the parameters of clock polarity ( CPOL ) and clock phase ( CPHA ). At CPOL Clock = 0 is the low idle, in CPOL Clock = 1, the Idle High. CPHA now indicates the data should be transferred to the umpteenth edge. When CPHA = 0, they will be taken at the first edge after SS has been pulled low when CPHA = 1 in the second. Thus, the data with CPOL = 0 and CPHA = 0 taken with the first edge, which can only be a high edge. When CPHA = 1, it would be the second, ie a low edge. When CPOL = 1, it is therefore exactly the other way around, with CPHA = 0 and CPHA low edge = 1 high edge.

The slave sets with CPHA = 0 to its data even when pulling down of SS MISO so that the master can accept the first change. When CPHA = 1, the data set from the slave until the first transition edge on MISO so that they can be adopted by the master on the second edge change. The master, however, focuses its data to always at the same time, usually shortly after the falling edge of SCK.

With each clock period, a bit is transmitted. In the usual Bytetransfer ie eight clock periods for a full transmission can take place. It can also be transmitted several bytes after each other with not defined in the specification, if the SS signal has to be briefly pulled high again between each byte. A transfer is ended when the Slave Select signal is finally set to high.