Through-silicon via

The term silicon - via ( english through- silicon via TSV ) is understood in the semiconductor industry usually a vertical electrical connection of metal ( engl. vertical interconnect access, VIA) through a silicon substrate (wafer, chip). The TSV technology is a promising option for providing electrical connections between chips part in the 3D integration of future integrated circuits (IC).

Application

In a 3-D integrated circuit ( 3D IC) is an integrated circuit, consisting of a vertical stack of individual chips thinned. He appears outwardly as a monolithic circuit, but strictly speaking, more of a hybrid circuit of far more cohesive than typical hybrid circuits. Overall, one would like to achieve an even higher functionality of the ICs in the same package footprint with these 3D integration. The via using TSVs, connecting the individual chip layers in 3D ICs. TSV in this case represents the currently most promising technique (short, robust, etc. ) to meet the high demands on the electrical paths, see also ITRS 2009.

Another application is the so-called 3D - case ( system -in-package, multi-chip module, etc.), they contain two or more ICs, which are space-saving stacked vertically. An alternative variant of a 3D body is IBM's "Silicon Carrier Packaging Technology ", in which the ICs are not stacked, but a carrier substrate was provided with TSVs and is used to connect several ICs in a housing together. But in most cases the 3D stacked chip are therefore not connected by electrical connections on the sides; Wiring technique somewhat increased the length and width of the package and generally requires an additional " interposer " layer between the chips. The wiring on TSVs have this wiring replaced on the sides opposite vias to make distributed over the chip surface, the vertical connections. The primary advantages are more robust connections and a further reduction in building heights. A disadvantage may be the loss of chip area by the additional TSVs. This technique is sometimes also referred to as through-silicon stacking or thru silicone stacking (TSS).

Swell

• Applied Materials Leads the Way to Enable TSV Interconnects for 3D Chip Stacking. Business Wire, July 12, 2010 ( press release by Applied Materials )