Triple-level cell

TLC memory cells ( TLC for short English triple - level cell ) are memory cells of the NAND type flash memory cell which can store per 3 bits (referred to in English as the level in this context ) ..

TLC memory cells belong strictly to the group of MLC memory cell (MLC short for multi - level cell, more than 1 bit per cell). In most publications, in which the new TLC memory are compared with the SLC and existing MLC memory, however, the MLC memory cell is in principle as a two -bit memory cell (also called 2-bit MLC memory cell ) is assumed.

Storing more than two states in the cell is achieved, in which (instead of only 2 or 4) of the floating gates of different charge levels can be distinguished in the writing and reading of the floating gate transistor 8. This makes it possible to accommodate more data in the same number of memory cells, whereby the prices for TLC chips compared to SLC and the 2-bit MLC chips may be smaller by a multiple. With increasing bit density of memory cells, however, also increases the risk of failure of a cell due to increasing the bit error rate ( Bit Error Rate Data Sheet, BER). In addition, such processes are much more difficult to implement error correction than SLC or 2-bit MLC memory cells. This extends the life of memory cells TLC compared to SLC and the 2-bit MLC cells is significantly lower.