WinChip

WinChip is the name of a processor family for Socket 7, which was developed by Centaur Technology and sold by IDT. The CPUs were thereby developed with the focus on the best possible production costs. This required that the area be as small as possible, which meant that the architecture had to be kept very simple. The WinChip CPUs were therefore not particularly fast, but had a very low power consumption, low heat and very few mistakes.

In Germany, these processors were not allowed to be traded under this standard international name, however, as an enterprising fellow man in Germany before IDT these had protected it and a Munich law firm in June 1999 led one of the first mass warnings of the Internet age. IDT sold the CPUs in Germany, therefore, only with the shortened name C6, W2 and W2A.

  • 2.1 IDT C6 WinChip
  • 2.2 IDT WinChip 2
  • 2.3 IDT WinChip 2A
  • 2.4 IDT WinChip 2B
  • 2.5 IDT WinChip 3

Models

WinChip C6

In 1997, the IDT WinChip C6 was put on the market. The C6 had a very simple design and was by and large only a " reamed " 80486th all advances of modern CPU architectures, such as out-of- order execution, branch prediction, return stack, or the like have been deliberately omitted to the architecture as simple as possible shape. Nevertheless, the CPU was thanks to the MMX technology and the very moderate power consumption (despite Single -voltage passive cooling at 240 MHz was easily possible) an asset to the market.

The execution speed was very below average and in integer range (integer) at the level of the Intel Pentium MMX, the floating-point performance ( FPU) was not competitive. Since the CPUs no more power supply required ( " Split Voltage Main Boards" ), they were without any major problems in older Socket 5 motherboards run and could thus be used as a relatively cheap Upgrade CPU.

WinChip 2

1998 was then presented as the successor of the IDT WinChip 2 (C6 ). The WinChip 2 was an improved C6, including the number of FPU and MMX units was doubled and added a branch prediction. These measures increased the speed of execution ( "performance" ) noticeably, so that the WinChip 2 much better could exist over the competition as yet the WinChip C6. Against the AMD K6 -2, however, had clearly at a disadvantage, they positioned the WinChip 2 so as a direct competitor for the Cyrix MII & 6x86MX. In addition, the WinChip 2 was the first CPU on the AMD K6 -2, which dominated 3DNow. Since a better (smaller) manufacturing technique was used, the CPU could be produced as cheaply despite the improvements as its predecessor. Also the WinChip 2 was suitable as Upgrade CPU for Socket 5 motherboards since it is still no "split- Voltage" required.

WinChip 2 A / B and 3

From WinChip 2, there was still the slightly modified versions 2A and 2B, each brought only minor changes. So supported the WinChip 2A FSB with a clock of 100 MHz (Super socket 7), and in addition non-integer multipliers ( x2, x2 and 33, 66) to enable clock frequencies of 233 or 266 MHz. The WinChip 2B needed then the first Centaur CPU Split -voltage motherboards; of course, were the changes in the WinChip 2A integrated. The next stage of evolution then stood at 1999, the IDT WinChip 3 with a 64K enlarged to 128 KB L1 cache. Other changes in the architecture were not provided.

The WinChip 3 but came to the prototype status not extend as Centaur Technology was sold in mid-1999 at VIA Technologies. Instead of WinChips 3 was marketed as the VIA Cyrix III CPU next to the market.

Model data

IDT C6 WinChip

  • L1 - Cache: 32 32 KB ( data instructions )
  • MMX
  • Socket 7 ( base 5 problem )
  • Single - Voltage
  • Special features: very simple RISC architecture
  • Front Side Bus: 60, 66 and 75 MHz
  • Release Date: October, 1997
  • Manufacturing Technology: 0.35 micron IBM and IDT
  • The size: 88 mm ² at 5.4 million transistors
  • Clock rates: 180, 200, 225 and 240 MHz

IDT WinChip 2

  • Codename: W2, C6
  • L1 - Cache: 32 32 KB ( data instructions )
  • MMX, 3DNow
  • Socket 7 ( base 5 problem )
  • Single - Voltage
  • Special features: very simple RISC architecture
  • Front Side Bus: 60, 66 and 75 MHz
  • Release Date: September, 1998
  • Manufacturing Technology: 0.35 micron ( 0.25 micron later ) at IBM and IDT
  • The size: 95 mm ² (58 mm ² at 0.25 microns ) at 5.9 million transistors
  • Clock rates: 200, 225 and 240 MHz

IDT WinChip 2A

  • Codename: W2A
  • L1 - Cache: 32 32 KB ( data instructions )
  • MMX, 3DNow
  • Super Socket 7 (100 MHz FSB)
  • Single - Voltage
  • Special features: very simple RISC architecture
  • Front Side Bus: 66 and 100 MHz
  • Release Date: March, 1999
  • Manufacturing Technology: 0.25 micron IBM and IDT
  • The size: 58 mm ² at 5.9 million transistors
  • Clock rates: PR200: 200 MHz
  • PR233: 233 MHz
  • PR300: 250 MHz

IDT WinChip 2B

  • Codename: W2B
  • L1 - Cache: 32 32 KB ( data instructions )
  • MMX, 3DNow
  • Super Socket 7 (100 MHz FSB)
  • Dual Voltage
  • Special features: very simple RISC architecture
  • Front Side Bus: 66 and 100 MHz
  • Release Date: March, 1999
  • Manufacturing Technology: 0.25 micron IBM and IDT
  • The size: 58 mm ² at 5.9 million transistors
  • Clock rates: PR200: 200 MHz
  • PR233: 233 MHz
  • PR300: 250 MHz

IDT WinChip 3

  • Codename: W3
  • L1 - Cache: 64 64 KB ( data instructions )
  • MMX, 3DNow
  • Super Socket 7 (100 MHz FSB)
  • Dual Voltage
  • Special features: very simple RISC architecture
  • Front Side Bus: 100 MHz
  • Release Date: not published for sale to VIA Technologies
  • Manufacturing Technology: 0.25 micron IBM and IDT
  • The size: 75 mm ² at an unknown number of transistors
  • Clock rates: PR300: 250 MHz
Integrated Device Technology Instruction set Microarchitecture Floating-point unit Cache (computing) VIA C3 List of microprocessors VIA C7 VIA CoreFusion
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