AMBA High-performance Bus

The Advanced High-performance Bus ( AHB) is part of the Advanced Microcontroller Bus Architecture ( AMBA ) IP manufacturer ARM Limited (ARM).

The CSO support:

• Multiple bus masters
• Burst transfers
• Split transactions
• Pipelined operations
• Single-cycle bus master handover
• Single clock operational
• Non- tristate implementation
• Large bus widths ( 64/128 bit).

Here AHB replaced in new systems older ASB whose functions is less.

A simple transaction on the AHB consists of an address phase followed by a data phase, that lasts without wait states only two bars. Here, the access is controlled to the target device via an arbiter means of a Mux (non- tri-state ) so that only one bus master has access to the bus.

Access to the Control Bus in the address phase and the data in the data phase is successively assigned independently, so that in the same clock phase one bus master can create the address and control lines, while a second master reads or writes data ( pipelined operations ).