AMD K10 (aka "AMD Next Generation Processor Technology " or "stars" ) is the code name of a micro-architecture for microprocessors from AMD, which has the K8 and K9 - generation supplemented and replaced the medium term. The K10 micro-architecture is still based on the AMD64 microarchitecture used for some time.
The K10 microarchitecture, formerly known erroneously as AMD K8L, but this is the code name of a low-power variant of the K8 microarchitecture.
The K10 microarchitecture is designed from the ground up as a multi-core processor.
On a The up to four cores were housed with their dedicated (ie dedicated ) caches up to two memory controllers, crossbar and from all cores shared 2 MiB large L3 cache in the manufacture in 65nm process.
With the changeover of production to 45nm now up to six cores were realized and the L3 cache is increased to up to 6 MB. At the same time, there is now also models without L3 cache.
45nm CPUs with the L3 cache cut in IPC ( instructions per clock) better than their 65nm predecessors, while CPUs have a lower IPC on average without L3 cache.
Compared to the crossbar K9 had to be extended in order to respond more cores.
The memory controller had to be adapted to the modified cache hierarchy and optimized.
Due to the shared L3 cache, the cores can communicate without going through the relatively slow main memory together normally. A detour is in these processors only necessary if the shared cache is not sufficient or the data for other reasons has already been transferred to the main memory.
A revised floating point unit is to increase the Gleitkommadurchsatz strong. Furthermore, advanced power management techniques with separate supply lines for the individual processor cores and the memory controller ( "split power planes" ) and a faster HyperTransport link (version 3.0) on newer motherboards are available. Maturity the advanced power management techniques are, however, only at the 45nm models, the 65 -nm models could not convince in idle compared to the K9 generation.
Due to the extensive changes at the processor interface and the power supply socket introduced new processor for the K10 - generation. For motherboards with a processor this is the AM2 socket, or the socket AM3 DDR3 unless you want to use as a work area and it is a newer 45nm CPU. However, there continues to be to use the limited possibility, the new generation with reduced function and possibly scope (eg, higher power consumption) in the older processor sockets AM2 and Socket F, if a BIOS update was provided by the motherboard manufacturer.
Differences to the K8 architecture:
- Advanced Instruction Queue: The Instruction Queue ( command queue ) is used for predictive storing the instructions. Instead of 16 bytes per clock cycle 32 bytes per clock cycle are possible.
- Improve branch prediction: Advanced branch prediction ( Advanced Branch Prediction) now with 512 entries and doubling the return stack.
- Sideband Stack Optimizer: This is new and leads stack optimizations for POP / PUSH - operations.
- Improving the TLB: The Translation Lookaside Buffer (TLB ) 1 GiB now supports large pages. A processor core with K10 architecture addresses the memory now with 48 bit versus 40 bit at K8. The addressable memory area is now up to 128 TiB. According to AMD, the working speed is increased due in large databases and virtual environments.
- Introduction of SSE4a or SSE128: per clock cycle and core reading of two 128 -bit SSE instructions is possible. Thus, up to four floating-point operations in double precision per clock cycle are possible. In the K8 architecture of the SSE path is " only " 64 bits wide. In addition, there are new SSE4a commands: EXTRQ, INSERTQ, MOVNTSD, MOVNTSS. Furthermore, the SSE instructions for bit manipulation to be extended: LZCNT, POPCNT.
- Independent Memory Controller: Through an independent memory controller more DRAM banks are possible, there will be less conflict - Page and are larger burst lengths possible. The Write Bursting to bundle multiple read and write accesses to the memory and run in a single pass. This is to increase the effective memory throughput. In contrast to the K8 and K9 K10, the two memory channels that can be independently drive ( " unganged " mode). Thus, the CPU can read and write access to the memory.
- L2 - Cache: The data connection between the processor core and L2 cache has been increased from 128 bits to 256 bits.
- Shared L3 cache: all cores have access to the shared cache.
The desktop processors the K10 - generation (AMD Family 10h Processor) are marketed under three instead of two brand names. The models with an L3 cache to be marketed under the new product name Phenom, those without L3 cache than Athlon. In addition, no longer based as recently been the AMD Athlon X2 the designation system on the Quantispeed rating, but on a structured type, number, similar to the AMD Opteron.
The first Phenom series with four-digit model numbers was presented in November 2007 (at that time still under the name AMD Phenom X4 without the addition ). End of March 2008 was followed by the three- core processors with the name Phenom X3, in October 2008 based on Athlon models.
In early 2009, the AMD Phenom II and a little later of AMD Athlon II was presented. These carry three digit model numbers and are manufactured in a modern manufacturing process, reducing the power consumption drops significantly and substantially higher clock speeds were possible.
In the Server field of Successful Product Name AMD Opteron is maintained, first products with the quad-core processor "Barcelona" were brought on 10 September 2007 on the market.
First processors with an integrated graphics processor, called APUs (AMD Family 12h Processor ) also have processor cores based on the K10 Archiektur. These CPUs / APUs are summarized under the concept of fusion AMD, but do not perform marketing name in the processor name. The APUs are only divided A4, A6, A8 series or in series such as AMD.
Processors of the K10 microarchitecture
The following processor families AMD based on the K10 microarchitecture: