Analog-to-digital converter

An analog -to-digital converter (ADC, engl. ADC for Analog -to- Digital Converter ) and Analog - to-digital converter or A / D converter is an electronic device or component for converting analog input signals into digital data and a data stream can then be further processed or stored. A plurality of relaying method in use. The counterpart is a digital -to-analog converter (DAC ).

Analog -to-digital converter are elementary components of almost all devices of modern communication and consumer electronics such as mobile phones, digital cameras, and camcorders. In addition, they are used in the data acquisition in industrial applications, machinery and technical everyday objects such as cars or household appliances.

• 2.1 Zero error, gain error and nonlinearity error
• 2.2 Error in the staging
• 2.3 Temporal and aperture error

• 3.1 Stepwise converter ( counting method ) 3.1.1 Single - slope converter ( Sägezahn-/Einrampenverfahren )
• 3.1.2 Dual and Quad slope converter (multi- ramp method )
• 3.1.3 charge balance converter

• 3.2.1 caster converter
• 3.2.2 Successive Approximation 3.2.2.1 weighing method
• 3.2.2.2 Redundant converter

• 3.3.1 Real -parallel converter
• 3.3.2 Pipeline converter

Function

The ADC quantizes a continuous input, such as electric power, both in time and in the range of values. Each signal will be characterized by the reaction in a signal -time diagram in a sequence of points with stepped horizontal and vertical intervals, at the main parameters of ADCs are its resolution and its implementation duration of which depends on the maximum sampling rate.

The resolution determines the maximum accuracy with which the input signal can be discretized. The accuracy is usable by other sources of error of ADUs even lower. The reaction time is often constant, but may depend depending on the realization method of the value of the applied voltage. In addition to the fastest possible method, there are also slow (integrating ) method for suppressing noise interference.

Timing quantization and aliasing

Each AD converter needs to implement a particular time. The shorter it is, the higher may be the sampling frequency. The choice of a suitable sampling frequency must be observed in addition to the fundamental frequency of the substantially harmonic oscillations of the expected input signal.

To be able to fully reconstruct the signal later, the sampling frequency must be greater than twice the maximum frequency in the input signal. Conversely, the input signal must be bandlimited; Signal components having higher frequency than half the sampling frequency have to be as closely as possible prior to the reaction is suppressed by a lowpass filter. Otherwise, there is a sub-sampling, which initially does not allow correct reconstruction more.

Sometimes the signal to be sampled is, however, so high frequency that you technically can not realize this condition. However, when the input signal is periodic, we can provide via multiple sampling with a time delay but a reconstruction without violating the sampling theorem as in multi-pass of the signal between points are determined so that a larger number of sampling points is produced what, in effect, an increase in sampling rate corresponds.

The input signal shall not, in many conversion methods during the signal conversion does not change. Then, on the actual front of the AD converter, a sample-and- hold circuit ( sample-and- hold circuit ), the signal value (English sample) as buffers analogous to that it remains constant during the digitization. This is particularly true for the gradual and bitwise converter that require longer transfer times. If a converter requires this sample and hold circuit, so it is usually included today at realization of an integrated circuit.

In the ideal case, the AD conversion is held in always exactly equal intervals. Due to random variations of the distance, however, has an effect which is referred to as jitter. He distorts the original signal during the subsequent reconstruction, as these equidistant again - that is, with equal intervals of time - is done.

Value-based quantization

The quantization limited by the number of Quantierungsstufen the resolution of the input signal; the output it shows itself in the increment to the least significant digit ( least significant bit - LSB). The resulting consequence of the quantization of deviation is called quantization error. In an ideal analog to digital converter to win with each additional bit - that is, for each doubling of the number of quantization intervals - a signal to noise ratio of 6dB. In addition, an ADU is subject also to the thermal noise.

Also of importance is the dynamic range, the ratio between the largest and smallest representable value. This is usually expressed in decibels and is in an 8 -bit ADC only 48 dB, which is about the sound quality of a compact cassette. A CD stores bits per measurement point 16 and thus achieves a dynamic range of 96 dB.

When digitizing speech or music, it is found that at low volumes the quantization noise is prohibitively large. Therefore, the analog signal is often pre-distorted (see A-law process and Dolby ). With the method of the 13-segment characteristic can save the results of a 12 - bit conversion with 8- bit data words, with no audible degradation.

Reference value

Since the ADC supplied analog signal is converted to a size less digital value, it must be evaluated with a predetermined value or signal (input signal range or range). In general, a fixed reference value Ur is ( an internally generated reference voltage, for example ) are used. The analog input signal is mapped digitally, the reference specifies the allowable peak value of the input signal.

Quantization

In an ideal analog -to-digital converter preferably is a linear relationship between input and output. There are

And besides other encodings, such as two's complement, BCD code can be used.

Further, there are AD- converter with non-linear quantization, for example, by the logarithmic A-law and μ -law A method for telephone networks.

Basically, a two-quadrant multiplication or modulation is possible with a variation of the reference value, wherein, in contrast to the DA converters of the range of the reference voltage may vary to a lesser extent.

Deviations

In addition to the quantization errors are more observed.

Zero error, gain error and nonlinearity error

As variations in the characteristics between the real and the ideal converter following errors are defined (see picture):

• Zero error (offset)
• Gain error (English gain error )
• Nonlinearity error

The gain error is often expressed as a fraction of the current value, the zero-point error with the quantization and the non-linearity error of the final value as a fraction or a multiple of the LSB.

Error in the grading

Individual steps can vary widely.

With continuously increasing input size, it may occur depending on the production method that a value of the output variable is skipped, especially if there is a carry over a number of binary digits, for example 0111 1111 after 1000 to 0000. Spoken purpose of "missing codes".

Temporal and aperture error

When digitizing a sinusoidal voltage produced by temporal variations of the clock? T (clock jitter ) and variance of the circuit, a frequency proportional to the input errors. The maximum allowable jitter at a resolution of the ADC q can be calculated as: .

Realization process

There are a large number of methods that can be used for converting analog to digital signals. The most important principles are listed. As an input variable, the voltage is taken as a basis for all examples.

The inner workings of a reaction control the building blocks themselves. For working with a computer is a ADC can be provided with a start input for the request for a new implementation with a "busy " output for reporting the ongoing implementation and with bus compatible data outputs for the readout of the resulting digital value.

Stepwise converter ( counting method )

In the counting of the smallest adjustable step is so long ( one LSB respectively) added to an intermediate value, and this is compared by a comparator to the input size, until he reached as concise as possible. There is a method in which a counter up or down follows all changes of the input signal, as described later in tracking converter. Most methods build the count starting at zero in a periodic repetition scratch.

Single-slope converter ( Sägezahn-/Einrampenverfahren )

When the output voltage of a sawtooth Sägezahnverfahren two comparators K1 and K2 are connected to the ground potential (0 V) and with the ADC input voltage is compared. During the period in which the sawtooth passes through the range between 0 V and the voltage pulses of the quartz oscillator are counted. Due to the constant slope of the ramp is the elapsed time, and thus the count in proportional to the height reached by the ADC input voltage. At the end of the count, the count is transferred to a register and available as a digital signal. Then the counter is reset, and a new reaction process begins.

The reaction time of this ADC is a function of the input voltage. Fast changing signals can not be detected with this converter type. Converter after Sägezahnverfahren are uncertain, because the ramp works with the help of a temperature- and age- dependent integration capacitor. They are used because of their relatively low circuit complexity for simple tasks, such as game consoles, to digitize the position of a potentiometer, which is moved by a joystick or a steering wheel.

Dual - and quad- slope converter (multi- ramp method )

Dual - and quad- slope converter essentially consist of an integrator and more counters and electronic switches. The integrator operates with an external high quality capacitor, which is in two or more cycles of charging and discharging. The dual-slope method, the integrator input the unknown ADC input voltage is initially connected to the load and there is a fixed predetermined time interval. For the subsequent discharge of the integrator is connected to a known reference voltage of opposite polarity. The required discharge time until the zero voltage at the integrator output is determined by a counter; the count is immediately with suitable dimensioning for the input voltage. The size of the capacitance shortens out in this process from the result. To correct the zero error of the ADC, another charge-discharge cycle is performed with short-circuited integrator input in the four- ramp method yet. The reference voltage is the determining variable for the accuracy; that is, for example, that thermal fluctuations must be avoided.

Such converters according to the multi- ramp methods are slow, require no sample and hold circuit, and offer high resolution and good differential linearity and good suppression of spurious signals such as noise or Netzeinkopplung. The typical field of application is reading devices (digital multimeter) that require little conversion time under ½ s and at a suitable integration time 50 -Hz noise on mains frequency can eliminate superimposed.

Charge balance converter

When charge balance method (Charge- balancing method) of the an integrator capacitor is charged by a proportional to the input voltage electric current and discharged by short current pulses in the opposite direction, so that builds up in the middle no charge. The larger the charging current is, the more often is discharged. The frequency is proportional to the input size; the number of discharges in a fixed time is counted, and supplies the digital value. In his behavior, the process is similar to the dual- slope principle. Other analog input stages that include a voltage-frequency converter with high enough accuracy, perform a frequency count to a digital value.

With feedback converter ( serial process )

These work with a DAU, which provides a comparison value. This is approximated by an appropriate strategy for the analog input signal. The deadline for the DAC digital value set is the result of the ADC.

Caster converter

Here a counter is used for data storage. Depending on the sign of is incremented by one step up or down and re- compared - counted and new compared to the difference is smaller than the smallest adjustable step. These converters "drive" after the signal simply, wherein the reaction time depends on the distance of the current input signal to the signal at the last implementation.

Successive Approximation

These work with a DAU, which rebuilds a comparison value each time. The input signal is limited by means of intervals. Simple successive approximation relies per step by one bit. An order of magnitude more accurate and faster conversion can be achieved that the implementation is redundant, by reacting with a smaller step size, as corresponds to one bit.

Weighing method

A possible approximation is the weighing process. Here, in a data memory ( successive approximation register SAR) are initially set all bits to zero. Starting with the most significant bit ( most significant bit, MSB) are determined successively, all the bits of the digital value down to the least significant bit ( Least Significant Bit, LSB).

From the control unit, the bit in-process is tentatively set to one, respectively; the digital -to-analog converter generates the current digital value corresponding to a comparison voltage. The comparator compares the input voltage and causes the control unit, the bit in-process again reset to zero when the comparison voltage is higher than the input voltage. Otherwise, the bit is at least necessary and remains set. After setting the least significant bit is smaller than the smallest adjustable step.

The input signal is not allowed to change during the reaction, otherwise the low-order bits would be obtained on the basis of established but no longer valid high-order bits. Therefore, a sample-and- hold circuit ( S / H) is connected upstream of the input. For each bit of accuracy, the ADC requires each one clock cycle implementation time. Such converters achieve resolutions of 16 bits and a conversion rate of 1 MHz.

Redundant converter

The weighing method similar redundant analog -to-digital converter assume that no exact halving of the outstanding interval takes place around the target value around, but this interval is limited only to a portion thereof. For this they have a digital- to-analog converter, whose elements are not scaled according to the binary system, in other words always a factor of 2, but to a smaller factor. You take it one hand into account that more elements are needed to cover the same range of values ​​, but allow the other hand, that the converter an order of magnitude faster and more can achieve higher by several orders of magnitude accuracy: The faster function comes from the fact that the comparator at each step does not have to wait until his amplifiers have settled up to a multiple of the target accuracy ( always something on the order of as many attack time constants, such as the converter bits to implement ), but a decision after the incredibly short 50 - % settling time can deliver that in a fairly large area is faulty then within the remaining interval. But that will be more than absorbed by the redundant converter elements. The Gesamtumsetzdauer of such a converter is of the order of one order of magnitude lower than its simple role model. The redundant implementation process, such a converter has a much lower noise floor than its purely dual counterpart.

In addition, such an ADU Calibrate itself, namely to an accuracy which is limited only by the noise. By letting the Selbsteinmessen run much slower than the reaction in the practical application, the noise influence can be pressed in this process one order of magnitude. The resulting characteristic curve of such a converter is completely linear up to a noise-like deviation by a few multiples of the smallest element used in Selbsteinmessen. By two such converters are placed side by side on the same chip and is always self-calibration mode, such a converter can be made almost resistant to manufacturing tolerances, temperature and supply voltage changes. The achievable resolution is only limited noise. The noise is depending on the concrete implementation by about 10 dB above the noise temperature. The data rate can reach several 100 MHz.

Delta -sigma method

The delta-sigma method, also referred to as a 1- bit converter, based on the delta-sigma modulation. In the simplest form ( first-order modulator ), the input signal is an analog subtractor for integrator and causes at its output a signal which is evaluated by a comparator with one or zero. A flip-flop generates a binary signal from a discrete-time, which provides a 1 -bit digital -to-analog converter into a positive or negative voltage, which retracts back to zero via the subtractor integrator (control circuit ). A downstream digital filter converts the serial bit stream and high frequency data in low renewal rate, but high resolution ( typically 16-24 bits). In practice, delta sigma converter can be constructed as a higher-order systems, that is, by a plurality of serially disposed difference and integrator stages. This allows for better noise shaping and thus a higher gain in resolution with the same oversampling.

An advantage of the delta-sigma converter is that the dynamics can be mutually exchanged by the bandwidth within certain limits. Due to the continuous sampling at the entrance, no holding circuit (English sample and hold ) are required. Also low demands are made of the analog anti-aliasing filter.

The benefits are paid for by the disadvantage of relatively high latency, which is mainly caused by the digital filter stages. Delta -sigma converters are therefore used where continuous signal waveforms and only moderate bandwidths are required, such as in the audio field. Virtually all audio devices in the field of consumer electronics products such as compact disc players, SACD, DAT recorders use these converters.

Even with data converters in communications technology and the measurement technique is used increasingly because of falling prices. By doing necessary high oversampling the process at higher frequencies of a few MHz, however upstream limits.

Flash converter ( Parallel method )

Real -parallel converter

While the successive approximation performs multiple comparisons with only one comparator, the direct method or flash conversion comes out with only one comparison. For this, a separate comparator is implemented in flash converters but each possible output value (except for the highest ) is required. For example, an 8- bit flash converter thus requires 28-1 = 255 comparators. At higher resolutions the effort required increases dramatically, which is why flash converters are typically available only in small resolutions of about 4 to 10 bits.

The analog input signal is compared at the same time by all the comparators ( via a linear voltage divider formed ) Comparative sizes in the flash converter. Subsequently, through a code conversion of the 2n -1 comparator signals into an n bit wide binary code ( with n: Resolution in bits). The result therefore is after the run delay ( switching time of the comparators and delay in the decoder logic ) immediately available. As a result, flash converters are therefore very fast, but bring also generally high power losses and cost with it ( especially at the high resolutions ).

Flash converter normally come in all digital oscilloscopes and in the digitization of video signals for use. As an example, the MAX109 allows a resolution of 8 bits, a sampling rate of 2.2 GHz. In today's digital oscilloscopes with possible sampling rates of 20 Gigasample per second demultiplexer additionally be installed.

The code conversion requires regardless of the resolution only one column of AND gates and OR gates with a column ( see picture). It converts the result of the comparators into a binary number. She works with a very short and for all binary digits equal length cycle delay. For the four possible values ​​of a two-bit converter three comparators are required. The fourth has only the function to signal overrange and to support the code conversion.

Pipeline converter

Pipelined converters are multi-stage analog-to- digital converter having a plurality of separate steps, which are constructed in the pipeline architecture. Your levels are generally of flash converters on a few bits.

In each pipeline stage is a coarse quantization is performed again implemented, this value with a DAC into an analog signal and subtracted from the buffered input signal. The residual value is amplified is supplied to the next stage. The advantage lies in the greatly reduced number of comparators, for example, 30 for a two-stage eight-bit converter. Furthermore, a higher resolution can be achieved. The multi-stage increases the latency, but reduces the sampling rate is not essential. The pipeline converters have genuine parallel converter replaced except in extremely time -critical applications. This multilevel converters achieve data rates of 250 MSPS ( mega samples per second) at a resolution of 12 bit ( MAX1215, AD9480 ) or a resolution of 16 bits at 200 MSPS ( ADS5485 ).

The values ​​of the quantization levels are added taking into account their weighting. Usually a correction ROM contains calibration data which serve to correct errors which occur in the various stages of digitization. In some implementations, this correction data is generated on an external signal, and stored in a RAM.

Hybrid converter

A hybrid converter is not an independent converter, but combines two or more conversion methods, for example based on a SAR structure, the initial comparator is replaced with a flash converter. This multiple bits can be determined simultaneously in each approximation step.

Important parameters

• Sampling rate ( sample rate ) - an indication of the frequency of implementation.
• Resolution (Resolution ) - width of the steps (even number of stages or the number of digits) that are used to represent the output signal.
• Zero error - The converter characteristics ( excluding the grading) is moved. The digital value is different from the correct value by a constant amount.
• Sensitivity error, gain error - The converter characteristics ( excluding the grading) is rotated ( pitch error ). The digital value is different from the correct value by a constant percentage of the input size.
• Integral nonlinearity - the error in that a a linear underlying converter characteristic curve ( without consideration of the gradation ), is non-rectilinear.
• Differential non-linearity - deviation of the width of the implementation stages, with each
• Quantization - Graphical representation of the relationship between the digital output values ​​and the analog input values, such as a linear or logarithmic, following the run.
• Quantization - Due to the limited resolution induced deviation of the output signal from the functional ( steady ) course.
• Information gap (missing code) - If a continuous increase of the input signal has no consecutively numbered values ​​of the output code result, but a value is skipped; possible in a differential non- linearity by more than 1 LSB.
• Latency - the propagation delay from the detection of the input signal to provide the respective output signal.
• Signal -to-noise ratio in dB
• Dynamic Parameters
• Intermodulation distortion in dB
• Operating current - the faster relaying electronics must work, the higher is their supply current ( self-heating ).