Asynchronous circuit#Asynchronous CPU

Asynchronous processor architecture describes a hitherto little common design of processors, which does not require central clock. Instead of all components to provide a common clock signal, the processor of asynchronous circuits is established, the clock itself. These properties, in contrast to synchronous processor architecture, a lower power dissipation and higher robustness can be achieved in particular.

• 3.1 Asynchronous Processors

• 5.1 research

Operation

Individual asynchronous circuits as logic blocks together form an asynchronous processor. Each of these circuits consists of a logic unit as a data path and a control logic. The data path is responsible for the actual measurement, during which control logic controls the transfer of data between the individual components. This may take place when the logical unit has completed and are expected to provide the correct data in the output register. In addition, the next logic block must be ready to accept new data in the input register.

Delay models

As long as the calculations of a logic unit still running, the data at the output registers are not consistent and can therefore be invalid. There are several delay models to be done to transfer data from the output register at the right moment ( incomplete list ):

Bounded Delay Model

In the bounded delay model ( engl. "limited delay " ) is set a limit on the time delay for each data path. This delay is the maximum time required for the affected logic unit in order to complete their calculations. It is always the worst case (English " worst case " ) is assumed. That is, going from the lowest allowed values ​​for factors that influence the calculation time of. Such factors may, for example, temperature, power supply, or the structure of the data to be calculated.

For each data path, a control means of the control logic specific to this data path maximum delay time, data transfer to the next logic block. This is done via a delay element, the transfer, after the specific delay, triggers. Then, the subsequent component can continue to work with the data.

This model simplifies the design of asynchronous processors, as existing designs of logic units taken from synchronous processors and can be embedded into the bounded delay model. This also shows that there does not affect the asynchronous behavior, the calculations per se, but only the transfer of data by logic block to logic block.

The data transmission between individual bounded delay elements mostly regulate micro pipelines (English " micro tubing " ) according to the principle of Ivan Sutherland. These form the asynchronous interface between the components, by using a data path by bounded delay model. The transfer is triggered by a delay element. The logic for the transmission itself comes then from without estimates of delay times.

Delay insensitive circuits

In delay -insensitive circuits (English " delay- insensitive circuits " ) is, unlike the bounded delay model, not be assumed that the output data after a fixed period of time, be ready. Nevertheless, because a reliable data transfer is necessary to the stability concerns of the valid data is detected at the input of the receiver. This is realized with the aid of a special code ( such as dual-rail ) of the data, and a handshaking protocol ( for example, 2 - phase, dual-rail or 4- phase dual-rail ). Once the receiver has taken over all the data, the transmitter is this acknowledged by a receipt. The implementation of the handshaking protocol and the need for dual-rail encoding require enormous amounts of additional transistors (factor 2-10). Nevertheless provide delay -insensitive circuits advantages: You have a tremendous robustness against external influences, such as temperature changes, changes in the supply voltage or production variations, which can be reached either from other asynchronous circuits, nor of synchronous circuits.

Quasi delay insensitive circuits

Within the delay -insensitive model no general delay circuits can be developed. There are only Muller- C elements and inverter permitted. It is not allowed to continue to share the lines. To develop general circuits, the additional request was made that line divisions have to be isochronous, ie the signals must arrive at all ends of the line at the same time.

Dual -rail encoding

Using the dual -rail encoding, and an appropriate handshaking protocol, it is possible to detect the completeness of data. Thus, each bit is represented by two lines. This results in four possible combinations of which only two are needed for the actual data. The other two combinations are used for a null word, and an error state.

4- phase dual-rail handshaking protocol

This handshaking protocol found in delay -insensitive, or quasi- delay -insensitive circuits application. Together with the dual-rail encoding, it can ensure that only fully calculated and thus valid data is transferred. As the name suggests, 4 phases for the transmission are required:

• The initial state is that all wire pairs are set to 0.
• In the first phase, the data to be transmitted are applied to the output of the transmitter.
• In the second phase, the receiver accepts the data, if it is "free".
• In the third phase, the receiver signals the transmitter by an acknowledgment that it has accepted the data.
• In the fourth phase, the transmitter sets its output back to 0 A new cycle can begin.

Current sensing completion detection

When current sensing completion detection (English " statement of completion on current consumption measurement" ) (short: CSCD ) method is determined by measuring the power consumption of the affected logical unit the end of the calculations. This is made possible by the fact that the current consumption increases when switching the gate and decreases again to the quiescent level by the switching operation.

The problem here, however, that a reliable measurement is not always possible. If a few bits change, this can result in a low number of switching operations, whereby the power consumption is only minor. A minimum delay generator (English " minimum delay generator " ) for this case still has to be installed which triggers similar to the bounded delay model, the transmission. This is activated at the beginning of the calculations and solves the transfer after the longest expected switching time out.

Thus, a structure is given which can determine their timing itself, provided that the measurement of current consumption is successful. However, a disadvantage of this technique is the increased component count, as for current measurement and analog components must be installed.

Practical enforcement

Asynchronous processors are an area of ​​research and a stronger commercial distribution preclude especially the lack of experience and development tools. In addition, to provide synchronous technology for many practical problems integrating into an environment.

Asynchronous processors

As an example here are some representative called: