Berkeley RISC

The Berkeley RISC project was in the years 1980 to 1984 from the University of California, Berkeley, one on behalf of the Defense Advanced Research Projects Agency ( DARPA ) state research project carried out under the direction of David A. Patterson for the development of RISC - based ( Reduced Instruction Set Computer) processor architectures. From the project and its results, developed in a row commercial RISC microprocessor families such as Sun SPARC and AMD Am29000. Later processor architectures such as DEC Alpha and the ARM architecture were strongly influenced by the results.

General

The idea of ​​the project was based on the observation that most of the machines programs use only a fraction of the in - Archtikturen CISC ( Complex Instruction Set Computer) hardware available. The restriction to few and simple machine instructions in the context of RISC allows a simpler and faster chip design with a largely consistent powerful software.

The first project line was called RISC I, as gold, started in 1980 and was designed as a seminar on the topic of VLSI design. First results were published in 1981. The RISC -I processor model consisted of 44,500 transistors and was 31 machine instructions in 78 registers to process 32 bits each. The monitoring and control unit of the RISC I took only about 6% of the chip area while former CISC processors required approximately 50 % of the chip area for the control unit.

The second parallel line project launched RISC II, also known as Blue, was slower to the end of the project. Due to the slower course improvements over RISC I could be realized, including a pipeline and extended register set while reducing the chip size to 39,000 transistors. Furthermore, a new English Instruction Format expander has been integrated, which allowed specific machine commands in the external memory of 32 bits to 16 bits to reduce, said machine instructions are internally expanded to the full 32 bits. This allowed a better code density within the storage tank. The idea to found later use, among others, in the Thumb instruction set of the ARM processors.