Boundary scan

Boundary scan and boundary scan are synonymous terms for a standardized method for testing of digital and analog blocks in the electronics.

Due to the complexity and smallness of today's circuit designs, it is becoming increasingly difficult to physically gain access to certain points of a circuit. The interconnection of boards is increasingly performed via additional inner connecting lines. So-called multi-layer boards (English multilayer PCBs) can have up to 20 such wiring levels. In addition, Integrated Circuits (ICs ) with many pins are often delivered in enclosures that make a mechanical access impossible, since all connections are hidden under the chassis. It is therefore necessary to check circuit boards without direct physical access, as it is for example in an in -circuit test is necessary. Known as the Boundary Scan method has been developed primarily in Europe (Philips) and is now internationally standardized.

The boundary-scan method uses additional cells ( latches ), with the help of signals via predefined paths from the outside can be injected into the circuit to be tested. The signals from the circuit, which abut pins of the IC can be detected via the scan path. In normal operation, the latches are passive. There is no difference to ICs without boundary scan functionality; the terminals of the chip are connected only to the pins of the IC. In test mode, they are actively managed in accordance with the procedure.

To allow the use of the boundary-scan method in an integrated circuit, are incorporated in the inputs and outputs of highly integrated devices corresponding special modifications (at least). Here, a boundary scan cell is installed at each input or output of an IC. All the boundary scan cells are serially linked in a chain, which comprises the entire I / O structure of the integrated circuit. The IC has at least four specially reserved control and data pins. This is to test data input (TDI) and output ( TDO ), a test clock (TCK ) and a test mode select pin (TMS ) and the optional test reset input ( TRST ). These pins together result in the Test Access Port (TAP ). This is a synchronous finite state machine (german finite state machine, FSM ) with 16 possible states.

About TDI / TDO Test data will be passed. TMS is used to distribute control commands, which individually adjust the desired test mode for each integrated circuit. With the rising edge of TCK, the external data from TDI are read into the corresponding registers each. TRST is used to initialize the FSM.

The actual scan chain begins with the TDI input pin of the circuit. This is connected to the connector on the printed circuit board to the TDO of the boundary scan test device. The chain continues by connecting the TDO outputs of the individual ICs each with TDI of the next IC. At the end of the chain of the last TDO output is connected to TDI of the boundary-scan test device via the connector. TMS, TCK and TRST optionally be connected in parallel by all the ICs to the corresponding pins on the plug.

TDI and TDO are serial data on or pushed through a sliding function in the input scan cells ( the scan chain, see test scan ). If all TDI data are clocked in, they are output in parallel to the circuit under test arrangement. The response signal can then be detected by the output scan cells and read out serially. The scan cells are usually located on the I / O pins, which thereby can be circumvented. By the boundary-scan principle to avoid contacting a large number of pins and any associated contact failure and can easily reach ( part ) circuits within a chip. Usually, a plurality of scan chains (scan chains ) operating in parallel.

Using the Boundary Scan functionality connections between pins with Boundary Scan function can be checked. It is also possible to detect short circuits between these pins. With the aid of boundary-scan output cells and external programmable memory can be programmed. Typically, it involves flash memory. By going through the scan chain, this method is slower than other programming methods and is thus suitable only for smaller amounts of data. Nonvolatile memory can be checked by programming and then reading of bit patterns on the boundary-scan cells. This can also have their solder joints be examined. This method is used, for example in RAM memories.

The JTAG IEEE 1149.1 standard defines the specifications of the TAP bus and the scan cells. This standard is supplemented by the P1500 standard for backplane testing to test many different systems in an electronic device using the same interface.

Now the JTAG IEEE 1149.4 defined for the test of analog signals.

AC-coupled or differential signals can be tested using the 1149.4 JTAG standard IEEE.

Functional extensions

Beyond the pure test function offer many memory modules with Boundary Scan using the TAP bus also ways to program the relevant block in the circuit ( engl. in-circuit ). In microprocessors can run for debugging and troubleshooting via the most designated as JTAG interface connection and diagnostic programs. Thus, the use of special and most expensive in-circuit emulators is invalid. All of these extensions, however, are realized by special, mostly undocumented commands on the TAP bus and strong vendor-and block-specific.

Integration

Each test method has its limitations with respect to test coverage and fault detection or diagnosis. In addition, the increasing complexity of current and especially future assemblies. Designs such as BGA, Flip Chip uBGA or leave barely possibilities of mechanical access. To achieve optimal and maximum test depth, it is therefore useful to combine test methods to each other. Boundary Scan can be integrated as an option for the larger test and fault coverage in ATE systems such as in- circuit testers, flying probe tester, functional test systems or AOI systems.