A bus is a system for transmitting data between a plurality of subscribers over a common transmission path, wherein the subscriber is not involved in the data transmission between other nodes.
- 4.1 Addressing in parallel bus systems
- 4.2 Addressing in serial bus systems
- 6.1 First generation
- 6.2 Second Generation
- 6.3 Third Generation
- 7.1 bus
- 7.2 address bus
- 7.3 control bus ( control bus )
- 7.4 CPU internal bus
- 7.5 CPU external bus
- 7.6 computer - internal buses
- 7.7 Calculator external buses
For the origin and original meaning of the word "bus" There are several explanations, sometimes Backronyme:
- The abbreviation stands for Binary Bus Unit System.
- The word comes from the English ' bus bar ', which means busbar means.
Earlier buses were actually only parallel busbars with multiple ports. From this period ( from 1898 onwards ) the names come " omnibus bar" and abbreviated "bus bar " for such busbars (power rail). The label was made for data collection lines (data bus ) taken over, pass on the information to the connected devices.
The devices connected to a bus components are referred to as nodes or bus device. Nodes that are allowed to independently access the bus (in the sense of writing or send ), is referred to as active or masters, otherwise they are passive node or slave. A bus that allows more than one master node, called multi-master bus. In a multi-master bus a centralized or decentralized bus arbitration is necessary, which ensures that at any time only one master has the bus mastership. This is necessary because the bus can not only lose data by simultaneous write access, but also the hardware could be damaged. A centralized bus arbitration of the bus access is controlled by a particular component, the bus arbiter is called. The one node that initiates an access to the bus, called the initiator, the target of such ( read or write ) Zugriffes called target.
Depending on usage, a distinction is system buses, memory buses, peripheral buses and Ein-/Ausgabebusse. In addition, can in principle be distinguished from parallel serial buses.
Topology and scheduling
Whether something is a functional bus, does not depend on the physical topology. As often very high frequency electrical signals are transmitted on bus systems, occur at junctions reflections on what by interference at certain points and thus leads to malfunction of the whole system. Extinction to the signals Therefore, the linear topology is signally superior and most frequently encountered ( eg SCSI). Reflections at the line ends are prevented by termination. Termination by a termination resistor causes a high power dissipation, an RC member fluctuating idle level. More complex is the active termination, which sets the resting level by a voltage regulator.
Since the address and data buses require a large number of similar traces on a printed circuit board, one hand is a lot of space and requires a corresponding number of pins on the blocks, on the other hand may increase as the crosstalk and electrical problems. Therefore, there is as a solution approach to the halving this number by a bus phase, one half and the other half in another of the signals sent over the same lines ( multiplexed ). An additional control pin must then identify these bus phases. It is a time-division multiplex method. This was done in practice, for example, the address bus of the processor 8080 so and dynamic RAMs ( DRAMs), which leads to the RAS and CAS cycles.
Bus as part of the computer
In computer architecture, a bus is a subsystem that transfers data or power between computer components inside a computer or between computers. Unlike a terminal in which a device to another is connected via one or more conduits (Point-to -point connection ), a bus may connect several peripherals over the same set of lines with each other.
Modern computer buses may also be used for both bit -serial in parallel, as well. While in the actual network topology of the classic bus line all participants hanging side by side on the bus can be connected by suitable contacts node in a chain-like arrangement in a row. In addition to the network topology at the physical level, a busähnliches behavior are simulated by corresponding implementations (see OSI model with higher levels of transfer).
Most computers have internal and external buses. An internal bus includes all of the internal components of a computer to the main board ( and hence the CPU and the internal memory). Such an internal bus is also referred to as the local bus because he is meant to connect with existing devices in the computer itself, and not with those in other computers or external. An external bus closes accordingly external peripherals to the motherboard.
A bus system is always organized so that only a single node outputs data on the bus at any given time. In most cases the data is to be transported to a certain other node and processed by this ( Only in rare cases utilize a plurality of receiving nodes simultaneously the data sent, such as the CAN buses of an automobile ). To identify the target node addressing is performed, often specially arranged address bus.
Buses differ in the way in which individual nodes can be addressed. Both parallel and serial buses, there are a number of typical processes.
Addressing in parallel bus systems
A simple addressing scheme is as follows: only a single component is a bus master (typically this is the processor ), all others are passive. Sets the master now, an address on the address bus, so it is decoded by a central address decoder. This determines the addressed component and shares this with a select line that it is the addressed component. The actual data is then sent separately via the data bus.
A modification of this scheme arises when no central address decoder is used, but each connected component has its own address decoder has. The individual address decoder then decide on the basis of the applied address independently whether their component is the intentioned or not.
Another principle works without any separate address lines. According to the multiplexing shown above, the address is first transmitted over the lines. Now, ( as described above ), for example by address decoder addressing take place - which are now the partners have to remember the address, since the lines are used for other purposes after the end of the address phase, and consequently the address is no longer on the bus.
A modification thereof is used in the SCSI bus. Before addressing ( in SCSI jargon Selection phase called ) an arbitration takes place phase. In this case, each component reports that wants to use the bus, on the data line with its own address ( SCSI ID) corresponding number. Thus, although the number of possible addresses is limited to the number of parallel bus ( non-multiplexed address bus over the lines ), but this is done through prioritized evaluation immediately a solution of a bus conflict, ie the situation that several components want to use the bus simultaneously:
The device with the highest address has the highest priority and is now the bus master ( initiator).
The methods described can also be combined. In addition, it should be noted that real bus topologies are usually far more complex than that assumed here. Thus, in a computing system in general different types of buses are connected to a bus hierarchy with each other, which differ in the type of addressing and are coupled to one another via bridges. Such bridges are capable of addressing one bus protocol to another dictionary. Also addressing specific aspects of multi-master buses were not considered here.
Addressing in serial bus systems
The data transmitted to serial buses can be used as data packets (or frames) consider, which are divided into several fields. A typical data packet has, in addition to the sender address, the recipient address of the packet. Connected components view the recipient field, and then decide whether to process or discard the packet.
Even serial buses can be naturally designed as a direct data lines from component to component. In this case the emitter and receiver arrays are unnecessary.
Busmastering means that the processor of a computer system temporarily take control of the bus to an adapter card, the so-called bus master making it. This bus master addressed independently in the sequence memory and IO ranges for the purpose of data transfer. So the bus master operates as a kind of bridge or as a stand-alone CPU. Thus, during such a secondary processor controls the peripheral bus, the CPU is usually capable of performing other operations in the system, provided that the necessary resources in direct access. Most of the bus to the memory is gone still partly usable, so there exists a time-sharing. This is particularly noticeable on modern multi-tasking operating systems, a very positive in the responsiveness noticeable, the busmaster activity is often coupled to an interrupt signal to the operating system. The adapter case has the sense to use specific tasks asynchronously to other tasks.
Not only caught the bus mastering on buses to the CPU of a computer, there are in the area of computer networks additional ways to make bus Arbiting:
- In the token-passing the currently active bus master holds a so-called token that is nothing more than a watch variable ( flag). Has he completed his mission, he passes on this token to a particular neighbor on the bus ( in computer network ). This is used mainly in Ring buses. If you have not physically do it with a ring bus, it is software issue, bringing the potential bus users in a well-defined and known to all order.
- Other buses (Example: CAN or Ethernet) are prepared from the outset that there may be collisions of multiple participants simultaneously attempting to send. It is then the additional task to detect such collisions ( collision detection ) and to enable meaningful. It belongs to the definition of the respective bus or computer network to determine the latter strategy. It is obvious that such a method is also applicable for wireless radio communications, there is accordingly also used.
And other memory devices have been placed on the bus at the same address and data pins, which the CPU itself is used, by parallel connection. The communication is controlled by the CPU which reads the data from the devices and the blocks of the memory. Everything was then cyclically by a central timer that controlled the operating speed of the CPU. Connected devices showed the CPU that they want to send or receive data by a signal sent to other CPU pins, which usually happened by a form of interrupt. For example, a disk controller has ( see Controller ) signals the CPU that new data were ready to be read, after which the CPU the data shifted by reading the memory at the terminal, which corresponded to the drive. Almost all early computers were assembled in this manner, starting with the S-100 bus in the Altair and up to the IBM - PC in the 1980s.
However, these "first generation" of bus systems suffered from the serious disadvantage that everything is working on the bus at the same speed and all equipment had to share a single clock. The operating speed of the CPU increase was not easy, because you had to also increase the speed of all connected devices. This led to the strange situation that had to be throttled very fast CPUs to communicate with other devices in the computer. Another problem was that the CPU was required for all operations, and so when she was busy with other tasks, the real throughput of the bus had drastically suffer. Another practical problem was that these early buses were put together difficult because they required a lot of jumpers to set the various operating parameters.
Bus systems, the "second generation " as NuBus were aimed at solving some of these problems. They shared the computer usually in two " worlds ", the CPU and memory on the one hand and the equipment to be connected on the other, with a bus controller in between. This made it possible to increase the speed of the CPU, without affecting the bus. This has also been reduced much of the burden for moving the data from the CPU and into the card and the controller because devices via the bus without involving the CPU could talk to each other. This led to much better performance in actual practice, but also required a much higher complexity of the devices in the computer. Further, this bus went the speed problem by simply chose a larger Datentransportweg, and so by the 8-bit parallel buses of the first generation to 16 or 32 -bit went over in the second. Another improvement was that software settings have been added, which reduced the number of jumpers or replace these.
However, the newer systems had a negative trait they shared with their former cousins : everything depended on the bus ( except the CPU), had to work at the same speed. Since the CPU was now isolated and could increase their speed without any problems, the working speed of the CPUs and the memory increased continuously at much faster than the bus, with whom they worked. The result was that the bus speeds were now much slower than necessary for a modern system, and the machine starved for data because they worked much faster than data could be transported back and forth. A very typical example of this problem was that video cards even the newer bus systems like PCI ran away quickly. So they departed from for graphics cards of the bus concept and introduced an exclusive, much faster connection (port) for the graphics card, the Accelerated Graphics Port (AGP). The next step, and state of the art end of 2005 in this development is PEG, PCI Express for Graphics with 16 lanes.
During this period also began an increasing number of external devices to use their own bus systems. When the drives were first introduced, they have been connected with a plug-in to the bus. That is the reason why so many computers connected to the bus slots ( slots) have. In the 1980s and 1990s because of new systems such as SCSI and ATA were introduced, and so most were empty slots in modern systems. Today there are in a typical PC to the five different bus systems in order to operate the various devices.
Later they went on to prefer the concept of the local bus compared to the external bus. The former refers to bus systems that have been designed to work with internal devices, such as video cards, the latter to connect external devices such as scanners. This definition was always inaccurate: IDE type of use is by an external bus; he will almost always be found within the computer.
Buses of the "third generation" are now on the rise, including HyperTransport and InfiniBand. They usually have the property that they run at very high speeds, which are needed to support memory and video cards as well as lower rates are possible in order to facilitate communication with slower devices, such as drives. They are also very flexible in terms of their physical connections, and can be used both as internal buses as well as to connect different computers together.
This can lead to complicated problems when it comes to service different requests, resulting in that the software comes to the fore when compared to the hardware design. In general, the third generation buses tend to look more like a network than a bus ( in the traditional sense ), with more demand for log information as in prior systems, and the possibility that multiple devices can use the bus simultaneously.
A data bus transfers data between computer components inside a computer or between computers. Unlike a terminal in which a device is connected with another device through one or more lines, a bus may connect several peripherals over the same set of lines with each other. In contrast to the address bus or control bus, the data bus is bi-directional (if one disregards the address bus during DMA operation).
The terms 4-bit, 8- bit, 16 -bit, 32 -bit or 64 -bit CPU called generally the width of the internal data path, such CPU. Usually, the internal data path is as wide as the external data bus. An exception is, for example, the Intel i8088 CPU. Here, the internal data path is 16 bits wide, while the external data bus is 8 bits wide, only. On graphics cards, there are even higher bus widths to increase the processing speed.
The name of a data bus is used in multiple context:
- With an emphasis on data: the differentiation from common terminals, such as the power supply
- With emphasis on the bus: for distinguishing the topology, such as direct point-to -point connections
- In parallel buses: to distinguish it from address or control lines
An address bus is in contrast to the data bus is a bus that only transfers memory addresses. The bus width, ie the number of interconnections, determines how much memory can be addressed directly. If an address bus has n address lines, memory locations can be addressed directly. In a system with 32 address lines so 4 bytes Gibibyte can ( a memory cell = 8 bits ) = to be addressed. In a 64 -bit system even bytes = 16 Exbibyte ( EIB ) can be addressed. In general, the address bus width is not physically in this run (see above for multiplexing). The specified 64 -bit system rather refers to the width of the data bus. However, a 64 -bit data are regarded as the address of another memory location ( indirect addressing).
This bus is unidirectional, and is driven by the respective bus master (see A. above). The latter is usually the CPU, but most of all DMA -capable devices can also take this bus when they are active. Typical sizes of the address bus are 8, 20 ( the Intel 8088 ), 24 ( the successor to Intel 80286 ), 32 ( as Intel 80486 ), 36 (Pentium 2 to Pentium 4), 40 ( Athlon ), 44 ( Itanium), and 64 bit.
Control bus ( control bus )
The control bus ( unidirectional) is a part of the bus system (bidirectional), which accomplishes the control (English control) of the bus system. These include the lines for the Lese-/Schreib-Steuerung ( direction on the data bus ), interrupt control, bus access, the timing (if a bus cycle is required), reset and status lines. Which of the lines are used in a bus, depending on the type and structure of the bus. In multi-master systems, in which more than one subsystem can take over the bus control, an arbiter is required as a decision-making body.
CPU internal bus
The internal CPU bus ( engl.: internal CPU bus) is used to communicate the internal units of the processor ( between tail, calculator and other tabs ), optionally also with the L1 cache.
CPU external bus
The external CPU bus ( engl.: external CPU bus) connects the processor (s ), ( L2 ) cache, memory and peripheral bus interface, and Front Side Bus ( FSB) called, or alternatively only with the chipset (or its Northbridge ) where those external elements are connected.
Computer - internal buses
These buses connect components within a computer, so for example the CPU to the graphics card and with various input and output components.
Computer external buses
These buses connect the computer to external peripheral devices. There are only meant such interfaces that really have bus character, that allow you to connect more external devices simultaneously, for example, the SCSI bus.
Bus systems are used in particular within computers and used to connect computers with peripherals, but also in the control of machines (fieldbuses ).
In automobiles, buses are used to connect the individual electronic system components of a vehicle. By this measure, the default and immunity should be increased. In addition, other electronic systems can be easily integrated and updating new software is easier. A bus system also makes it possible for a vehicle to " Mobile Office " to convert.
Bus systems are increasingly used in building, such as the European Installation Bus ( EIB). Using the bus system is the control of lighting, window and door monitoring, heaters, air conditioners and other equipment of a building possible. The installation of a bus system should already be taken into account as possible to the building design, as the system, especially the necessary cables and wires, plenty of space needed. Retrofitting could be associated with significant structural measures.