CAS latency

With the Column Address Strobe Latency (English, short CL or CAS Latency ), also known as memory latency, the delay between the addressing in a DRAM device and providing the data stored at that address data is referred. CL is the number of clock cycles, the memory device needs to process the data supplied during the CAS before accept further commands, or may notify the result. The higher the CL value, the more clock cycles are required for the processing, which the delay dependent thereon becomes greater.

The accelerating effect of lower CL timing but is usually overestimated. It is generally less than 5% and thus is not as noticeable to the user. However, many customers are willing to pay for extras such modules. The disappointing acceleration effect can be mainly explained by the increasingly effective and larger caches on the processors that are already catching about 90-95 % of all requests. Also note that there are also other latencies, which have an influence on performance.