Clock-Gating

Clock gating is a common method for electronic synchronous digital circuits, to circuit elements in each selectively turning on and off the clock signal and thus the average power consumption of the integrated circuit (IC) to reduce.

General

Synchronous digital circuits, such as common microprocessors consisting of a plurality of edge-triggered flip-flops, all of which are from a central clock signal to the system clock, is clocked. In general, not all functional units are in a microchip on each clock edge timing actually needed - for example, because it is waiting for external events or specific functional units for a particular task are not needed. In clock gating are at appropriate locations in the clock distribution network in the microchip called gates, English gates, provided which can prevent the clock feed-through pipe to the unused functional units.

The background is located in the CMOS technology, in which the digital circuits can be fabricated. This technology has greatly dependent on the switching frequency power loss - the higher the frequency, the higher the power loss, the clock is always on. By the clock-gating the average number of switching operations is reduced to not need functional units, which reduces the average switching losses of the entire circuit.

The actual shift in the clock gate has to be such that there is no glitch occurs.

Applications

Microprocessors

Microprocessors usually have one or more different depths " idle" states, which are activated by special machine instructions and place the microprocessor into a power-saving and reduced-power mode using clock gating. Microprocessors for mobile applications such as the OMAP3 have, in addition softwareinduziertem clock gating on its own circuit parts which are the current use of parts of the microprocessor, such as the use of the DMA - unit to recognize and is not currently required circuit parts such as the DMA controller by clock gating off temporarily.

Clock division

Clock gating can also be used for the targeted reduction of the processing speed, without the need for clock signals of lower frequency. The gate is driven periodically. Field Programmable Gate Arrays (FPGAs ) have taktflankengesteuertem per flip-flop to a clock enable input, which is a form of a simple clock gate. Is inactive, the clock enable flip-flop ignores the clock signal. Now, when the clock enable input connected periodically active only at every second clock edge, this results in a halving of the clock rate at the flip-flop.