Complex Programmable Logic Device

CPLD stands for Complex Programmable Logic Device. The technology of programmable ICs has been known since the 60s, as Harris Semiconductor brought out a block on which essential part was a programmable diode array ( Fuse Configurable diode matrix). In 1978, the first fully configurable logic blocks called PLA (Programmable Logic Array) came together PALASM programming language on the market.

CPLDs consist essentially of the following elements:

  • Programmable AND / OR matrix
  • Programmable feedback
  • Input block
  • Output block

Ein-/Ausgabeblöcke can fast memory, such as latches, D flip-flops or registers to be. In many modern PLDs programmable outputs are available, which can be defined states (active low, active high, tristate) assign. The AND / OR matrix as core can be assigned to any combinatorial logic.

A CPLD is made up of many SPLDs (simple programmable logic device ). These are called macrocells. The individual SPLDs are in turn interconnected via buses. The homogeneous structure allows an exact determination of the processing time, which constitutes the essential difference to the FPGAs. Another, but not fundamentally necessary difference is the configuration: By manufacturing in EECMOS Electronically erasable complementary metal oxide semiconductor, the program remains the configuration in the CPLD and does not have to be reloaded each time. This criterion of the configuration is not a key differentiator between CPLDs and FPGAs, but it is currently not yet technologically possible to accommodate the much more complex FPGA structures together with EEPROM cells as in a CPLD on a chip. The market located reconfigurable FPGA devices without external memory are currently ( mid 2007 ) so-called multi-die solutions. Thereby a plurality of semiconductor chips made ​​of different technology such as a conventional SRAM based FPGA, and a flash configuration chip be housed together in a chip package. Outwardly, no external memory is more then needed for the FPGA.

Due to the high number of inputs / logic block to CPLDs offer especially for the solution of complex, parallel combinatorial AND / OR logic, in which many inputs and outputs are needed. At the same time the number of required memory ( flip-flops ) should be low when using CPLDs, as per input or output pins usually only a single flip-flop stands as a register. Digital circuits, which require a lot of registers such as shift registers or digital counter, so can only be achieved to a certain degree in CPLDs efficiently.

With an increasing number of cells, the macro cells are combined with local lines to higher-level structures such as logic array blocks, LABs. However, these numbers vary depending on the manufacturer.

Manufacturers are eg Xilinx, Altera, Lattice, Actel, Lucent, Cypress, Atmel or QuickLogic.

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