Conventional PCI

Peripheral Component Interconnect, usually abbreviated PCI is a bus standard for connecting peripheral devices to the chipset of a processor.

Survey

There are several variations and applications of the standards (PC, industrial, telecommunications). The most common variant is mainly in the PC environment to use and is officially called PCI Conventional. Virtually every built since about 1994 IBM PC -compatible computer with usually two to seven slots for PCI cards equipped (except for miniature and mobile versions ). Even newer computers from Apple ( from 1995 to 2005, and later PCI Express) and workstations from Sun have a PCI bus. In the slots, a large number of different cards from different manufacturers are used, among other things, network cards, modems, sound cards and (older or second) video cards. Thus, a PC can be easily adapted to specific needs.

Version 1.0 of the standard has been defined by Intel in 1991. Intel did not support the VESA Local Bus ( VLB ), since this was tailored specifically to the 486 architecture and less throughput offered. In contrast, the PCI bus can be used in any architecture.

There are now three different standards:

  • Conventional PCI PCI 1.0, proposed by Intel in 1991
  • PCI 2.0, introduced by PCI-SIG 1993
  • PCI 2.1, decided in June 1995
  • PCI 2.2, decided in January 1999
  • PCI 2.3, decided in March 2002
  • PCI 3.0, decided in April 2004
  • PCI - X 1.0, decided in September 1999
  • PCI -X 2.0, adopted in July 2002
  • Originally known as 3GIO
  • PCI Express 1.0, decided July 2002
  • PCI Express 1.1
  • PCI Express 2.0
  • PCI Express 2.1
  • PCI Express 3.0

The PCI bus has the ISA bus and the short-lived VL-Bus, such as those found in older PCs replaced. However, a PCI - ISA bridge allows the connection of the ISA bus to the PCI bus. On the Pentium generation and later systems, this is the only way to connect ISA cards since it is the set outward system of the original PCs the ISA bus. The PCI bus meet the requirements for graphics, and other network interface cards over time.

However, he was not fast enough for the then emerging graphics card with 3D acceleration after some time. 1997 therefore established additionally the Accelerated Graphics Port (AGP). This is based on the PCI bus, but is implemented as a point-to -point connection with complementary side channels and has now been developed to 8 times its original transmission rate. For as good as any other expansion cards types PCI, however, remained still the standard, but is gradually being replaced since 2005 by PCI Express ( see below). Currently, the industry is trying to bring PCI Express 3.0 to market and publicize, the 690 is required by high-end graphics cards such as the Nvidia Geforce GTX to also exploit the bandwidth.

Unlike the ISA bus PCI allows the dynamic configuration of a device without user intervention. During the boot process, the system BIOS analyzed the available PCI devices and has the resources it needs to. This allows the assignment of IRQs, port addresses, and memory areas corresponding to the local conditions. For ISA cards, you often had to manually set by jumper to be used IRQ etc.. In addition, the PCI bus is the operating system and other programs, a detailed description of all connected PCI devices through the PCI configuration space available.

The PCI specification also provides for the physical design of the bus (such as the distance of the conductor tracks to each other), electric properties, and timing protocols. The devices or interfaces must not be accommodated necessarily on stock cards, but can also be located directly on the motherboard of the computer, the specification speaks of planar devices.

General PCI bus specifications

The PCI bus is a synchronous bus with 33.33 MHz ( = 30 ns per cycle) or after the 2.1 specification 66.66 MHz clock rate, ie 15 ns per clock. These values ​​are maximum values ​​, according to the specification, the clock can also be lower and also very variable, for example, to save power. Therefore, the bus has a clock line. All signals are transmitted only on rising clock edge ( Single Data Rate ). The signals can be controlled by CMOS drivers, so the total power consumption is relatively low. The bus can be equipped with up to 10 devices, with between master ( controller of the transmission ) and slave ( may need to data (or commands ) are waiting ) is distinguished. A master can even take control over processes on the bus when needed, which is advantageous especially for cards with high IO traffic, such as network cards or disk controllers. Devices include also housed on the motherboard devices that connect to the host ( PCI / host interface ) or a possibly existing ISA bus (PCI / ISA interface) to record. For more than 10 PCI devices per system more PCI buses can be integrated into the system via PCI / PCI interface (PCI - PCI bridge ). The data transfer takes place in parallel.

On the PCI bus always communicates a master to a slave. Most PCI devices can be addressed both as a slave can start transactions as well as the master. Through an arbiter, a master is chosen, then has control of the bus. He starts a transfer by asserting an address to the 32 data / address lines and a command to 4 command / byte lines. Data and addresses are transmitted over the same lines and separated from each other by time division multiplexing. An additional parity line allows the detection of errors.

CPU and memory are connected by a so-called host bridge by bus. Most transactions on the bus occur between this bridge and the rest of the peripheral devices. Theoretically, peripherals and communicate with one another, this option is only used very rarely and only optionally supported by most bridges. Since master-capable peripherals can access the host bridge as a slave, they are able to write directly into memory and read from it - the equivalent of Direct Memory Access (DMA).

Each slave can be allocated at boot time by the BIOS address ranges. About Manufacturer codes can be uniquely identified cards after booting. Then data are transmitted via the data lines, wherein the command / byte lines for selection of bytes can be used in the 32- bit word. 8- bit transfers and possible - a result, in addition to 32 -bit and 16.

In the most common PCI version with 32bit/33 MHz maximum of 32 bits, ie 4 bytes can be transmitted in each cycle, so that the maximum transfer rate 133 MByte / s ( 4 bytes in 30 ns). About Ready - lines, both the master and the slave signal that they are ready to receive data. If a master or slave is not ready, no data is transmitted, ie the transmission slows.

Normally, the master completes the data transfer. About a STOP signal, the slave can force an end of transmission. Another master can request the bus through the REQ, the current transmission to be stopped after a predetermined latency time, and the new master can take the bus.

The PCI bus requires a minimum of 47 (slave ) or 49 (Master) signals on the bus. As of version 2.1 of the specification, a 64- bit extension is defined, which broadens the data bus to 64 bits. In a 32-bit system and 64- bit devices to coexist and interact.

On the bus, there are four interrupt lines, so that each device can generate up to four different interrupts ( INTA to INTD ). The interrupt lines are not connected on the bus, but can be individually routed and assigned. Normally, only INTA will be used. However, this can be depending on the slot assigned to a separate interrupt or, if not enough interrupts are available to be shared between different maps. The of the ISA bus, which could often assign too little interrupts problems so are largely past.

Notes:

The PCI bus can supply the connected device with power. According to the specification, the delivered power per slot is 25 watts. Depending on the voltage difference in the maximum ampere values ​​were determined.

PCI bus signals

The type of inputs and outputs can be divided as follows:

Signals on the PCI bus - the # symbol indicates that the signals are Active Low.

PCI ID

Each device or plug-in card in a PCI bus has a unique hardware identifier (ID). This is composed of three parts, which are used for the identification of function ( class ID ), make and model (device ID ).

Class ID: Vendor ID: Device ID

For example:

0200:8086:10 b5

This is:

  • 0200 for an Ethernet Network Controller
  • 8086 for the Intel Corporation (the number is indeed hexadecimal, but the numbers would be in decimal notation for Intel's granddaddy of the x86 architecture )
  • 10b5 for the device 82546GB Gigabit Ethernet Controller ( Copper)

About the Class ID, the device is assigned to a particular group. This facilitates the identification of unknown devices.

Operations on the PCI bus,

After configuring all the devices by the BIOS, all devices can be addressed via a command protocol. This consists of the command, address, and a sequence of data.

On " Reserved " commands PCI devices may not react.

Basic PCI variants

  • PCI Conventional, allows bus widths of either 32 or 64 bit, transfers with 33 or 66 MHz clock ( 133-533 MBytes / sec)
  • PCI -X 64- bit version of PCI Conventional with 66, 100 or 133 MHz clock ( 533, 800, or 1067 Mb / s)
  • PCI -X 266 (PCI -X DDR / QDR ), PCI -X 266 MHz nominal clock ( 2133-4266 MByte / s)
  • Mini PCI, smaller and with only 32 bits, for notebooks etc.
  • PC Card or CardBus, external cards ( successor to PCMCIA), smaller design, 32 bit, notebooks etc.
  • CompactPCI, PCI fully electrically compatible, but with in the form of slots 3 and 6 U
  • PCI low-profile, half-height, 32 or 64 bits, see Table
  • PC/104 and PCI104, fully PCI compliant stack for computer
  • PCI Express, the default base for graphics and add-in cards (such as RAID controllers) used. Current version is 2.0 on a Hyper Bridge 3.0 ( 5200 MHz) communicates with 16 lanes, with the mainboard.
  • ExpressCard, external cards ( successor to the 32-bit PC Card ), PCIe compliant, smaller design, PCI Express 1x interface (1 Lane ) for notebooks etc.

Dimensions of the PCI variants

Coding of the contact strip

  • 3.3V compatible cards have a notch on the left ( direction bracket)
  • 5 V compatible cards have a notch on the right
  • Universal cards have both notches
  • Slots after PCI 2.x have a ridge on the right ( the side facing away from the bracket ). Although the PCI 2.3 specification does not support 5 - V cards and more, but these still fit physically in the slot. However, still some motherboards still support 5 - V cards in PCI 2.3 slots. This will only work with 33 MHz PCI clock. Consult → mainboard specifications.
  • PCI slots after 3.0 have a web ( direction bracket), so that only 3.3 V and universal card with the corresponding notch can be inserted on the left.

Other PCI variants

  • Extended PCI ( PCI -X)
  • PCI Express ( first 3GIO called [ input / output of the third generation ], abbreviation PCIe or PCI-E), in contrast to the PCI bus on the electrical level, a serial point-to -point connection, but the PCI signaling and - programming techniques in use and can be handled by the operating system and software such as PCI. Since 2004, PCI Express gradually replaced both PCI AGP. It is not compatible with PCI or AGP.

Power Management with PCI

The energy saving features of the PCI bus are part of an optional -to-implement specification, which is settled in time between the PCI versions 2.1 and 2.2. Each PM- enabled device has an additional 8 -byte field in the configuration space, on which it can say what power-saving modes it supports, and can be controlled accordingly. Each PCI device can be in one of four possible modes of operation (D0 -D3). The higher the number, the less energy the device. Even if a device does not know about the PCI power management modes it supports the D0 and D3, because these are equivalent to on and off. Whether and how much energy can be saved in the intervening modes, is at the discretion of the hardware manufacturer. A device can change " including" lying in a certain mode in all modes, as well as from each mode in the state D0.

Although you can manually bring, during operation, to another energy saving mode devices well, you will do in most cases using APM or ACPI a global energy saving mode for the computer, which is controlled by the power management of the operating system. In modes D1 and D2 is a suitably equipped PCI device the ability to create at any given time, a power so-called management event signal ( PME) to the bus, which is then forwarded to the power management of the operating system and used to may, at the request of the system again global " wake up", such as when a network card detects incoming data that needs to be treated.

Terms

  • Fast Back-to -Back: When all devices support this mode, the idle phase can be omitted between two PCI cycles. This increases the data throughput on the bus.
  • Special Cycle: Using " Special Cycle" can be sent broadcast messages (broadcast messages) to all connected devices.
  • Address Space: one of three address ranges - Memory, I / O or Configuration Space
  • Configuration Space: The " configuration space " is a storage area (256 or 4096 bytes for PCI -X and PCIe) every PCI device, which is used to identify and configure the device. The configuration space consists of a standardized header ( header) and additional device-specific data such as address ranges. The BIOS or the driver for a PCI device can configure to fit the device based on this data.

Stakeholders

Special Interest Group

In 1992 the Special Interest Group "PCI -SIG " was ( originally named "Peripheral Component Interconnect Special Interest Group " ) was founded. The task of the PCI -SIG is the management and development of the PCI standards. For PCI -SIG companies and organizations can become members. In 2007, there were more than 800 members.

PCI Industrial Computer Manufacturers Group

Founded in 1994, PCI Industrial Computer Manufacturers Group (PICMG ) is a consortium of over 450 companies that want to extend the PCI standard for use in industrial, medical, military and telecommunications. This resulted in specifications such as CompactPCI AdvancedTCA or.

639616
de