Direct digital synthesizer

The Direct Digital Synthesis or direct digital synthesis ( DDS short ) is a method in digital signal processing for generating periodic, bandlimited signals with virtually any finer frequency resolution. The method provides today besides the rational fractional phase-locked loop, the dominant method for the generation of signals is finely adjustable frequency and has found widespread use in communications and instrumentation.

The term DDS referred to in the technical vernacular and integrated circuits ( IC) that realize the complete hardware of a synthesizer according to the DDS method. The widespread use of such ICs has significantly contributed to the success of the procedure.

Function

Direct digital synthesis is based on a digital adder, combined with a register together with feedback that represents a memory for the phase angle and is shown in the adjacent figure. The specified bit widths in the figure are examples and illustrate the different word lengths in the individual stages.

This so-called phase accumulator adds cyclically per clock step, the left- supplied input value adjusts inversely proportional to frequency. The current counter status corresponds to a phase angle, and an overflow of the phase accumulator ( automatic return to zero ) corresponds to a full rotation of the phasor of 2 · π.

The part belonging to a certain phase value signal value is formed by another function that assigns a phase value of a signal value. For example, a sinusoidal ( harmonic ) signal profile is desired, this block provides the sine function represents the Figure can be carried out at low bit-widths in the digital circuit in the form of a calculated in advance ROM table. Alternatively, the output values ​​for a sinusoidal waveform can be calculated at runtime with algorithms such as the CORDIC algorithm in the circuit. If only one sawtooth wave needed (for example, a synthesizer ), the phase value can be output directly as a signal value, since the phase increases linearly within each period and then jumps back to zero. A triangle wave that can replace a sine for some applications, can be produce, by interpreting the phase value as a signed binary number ( two's complement) and calculates their absolute value.

The digital signal can then be fed to further processing steps, such as an analog output to the far right as shown in Figure digital to analog converter.

The achievable with the method of frequency resolution depends solely on the word width of the phase accumulator. A typical word length is 32 bits, so is the frequency resolution at 100 MHz system clock about 0.023 Hz with a maximum output frequency of theoretically half the clock frequency (50 MHz).

The quality of the output signal depends primarily on the quality of the clock generator, the lowest possible jitter and the accuracy of the digital - to-analog converter from. The higher the frequency ( splitter smaller ), the coarser is the scanning of the table, and the more important the DA converter downstream filter. In practice, a compromise between the bandwidth and the accuracy is close. In the frequency range below 100 MHz are, status 2008, realizing sinusoidal signals with spurious intervals of approximately 80 dB. DDS circuits with integrated D / A converters are now available with clock frequencies up to 1000 MHz (for example, AD9912 ).

The implementation of the DDS ( without analog converter ) can be very simple both in an FPGA, DSP or ASIC. By appropriate functional extensions of the DDS also an angular modulation ( phase noise ) or amplitude modulation of the output signal can be realized.