DLX

DLX the microprocessor is a hypothetical processor architecture, developed by John L. Hennessy and David A. Patterson ( the original designer of the MIPS RISC architecture and Berkeley ). He was in the - book Computer Architecture - jointly by both: A Quantitative Approach presented. The DLX processor is controlled by a RISC instruction set and has 32 ​​registers. There DLX simulators representing the different pipeline stages and graphically interpreted assembler instructions. These are used in some universities in lectures on hardware-oriented programming.

The term DLX

For the origin of the name " DLX " There are several possible historical explanations:

  • DLX as deluxe
  • DLX as a Roman numeral: 560 (average of the then conventional processor architectures: AMD Am29000, DECstation 3100, HP 850, IBM 801, Intel i860, MIPS M/120A, m/1000 MIPS, Motorola 88000, RISC 1, SGI 4D / 60, SPARCstation -1, Sun-4/110, Sun-4/260 )

Pipeline

The pipeline of the DLX processor consists of five stages:

The design of the DLX pipeline prevents the occurrence of Write - after - read ( write after read) and write - after -write conflicts ( write after write). Read-after -write conflicts (read after write) are not prevented.

Register meanings

  • R0 null; immutable
  • R1 reserved for the assembler
  • R2 -R3 function return values
  • R4 -R7 function parameters
  • R8 -R15 arbitrarily
  • R16- R23 register variables
  • R24 -R25 arbitrarily
  • R26 - R27 reserved for the operating system
  • R28 Global Pointer
  • R29 stack pointer
  • R30 register variable
  • R31 return address

Instruction formats

A DLX instruction is always 32 bits long. The different instruction formats define the division of the 32- bit instruction in the fields. In all three formats, the first 6 bits are always the opcode.

I- format

Commands of this format are load / store instructions, arithmetic instructions and conditional / unconditional jumps. The instruction is composed of a source register and a destination register RD RS1, an additional 16 bits for the immediate value are provided, which are used depending on the command type.

0 5 6 10 11 15 16 31   ==========================================   | Opcode | rs1 | about | immediate |   ========================================== Example commands: LW, SW, JALR

R format

This format is used to perform operations on registers to perform, while the source registers rs1 and rs2 executed with the register ALU operation func, and the result is stored in the rd register.

0 5 6 10 11 15 16 20 21 31   ==========================================   | Opcode | rs1 | rs2 | about | func |   ========================================== Example command: SLT, ADD, SUB

J- format

Commands of this format are jump instructions. The (dist ) view is simply added to the program counter.

0 5 6 31   ==========================================   | Opcode | dist |   ========================================== Example commands: J, JAL

Instruction set

Excerpt from the DLX instruction set without floating - point instructions:

Instruction Instruction meaning LB / LH / LW R1, val ( R2) Load byte / halfword load / load word LBU / LHU R1, val ( R2) Load byte unsigned / load halfword unsigned SB / SH / SW val ( R2), R1 Store byte / halfword store / store word LHI R1, # val Load high immediate ADD / SUB R1, R2, R3 add / subtract ADDU / SUBU R1, R2, R3 unsigned add / subtract unsigned ADDI / SUBI R1, R2, # val add immediate / subtract immediate ADDUI / SUBUI R1, R2, # val add immediate unsigned / subtract immediate unsigned AND / OR / XOR R1, R2, R3 And / or / exclusive or ANDI / ORI / Xori R1, R2, # val immediate And / or immediate / exclusive or immediate SLL / SRL / SRA R1, R2, R3 shift left logical / shift right logical / shift right arithmetic SLLI / SRLI / SRAI R1, R2, # val Shift -left log. / Right log. / Right arithmetic -immediate SLT / SLE / SEQ R1, R2, R3 set less than / less or equal than / equal SLTI / SLEI / SEQI R1, R2, # val Set less than / less or equal than / equal -immediate SGT / SGE / SNE R1, R2, R3 Set Greater Than / Greater than equal / not equal SGTI / SGEI / SNEI R1, R2, # val Set Greater Than / Greater equal / not equal -immediate BEQZ / BNEZ R4, name Branch equal zero / branch not equal zero J name Jump JR R5 Jump register JAL name Jump and link (save return address in R31 ) JALR R5 Jump and link register (save return address in R31 ) val: 16-bit value as the address offset or immediate value name: 16 or 26 bit address - distance literature

  • John Hennessy, David Patterson: Computer Architecture. A Quantitative Approach., 3rd Edition, Morgan Kaufmann Publishers, ISBN 1-55860-724-2 (English )
  • Brink Uwe Schulte, Theo Ungerer: microcontrollers and microprocessors, Springer- Verlag, Berlin 2007, ISBN 978-3-540-4680-1-1, page 49
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