Harvard architecture

The Harvard architecture referred to in the computer science concept for implementing a circuit particularly fast CPUs and signal processors. The instruction memory is logically and physically separated from the data store. The logical separation results from different address spaces and various machine instructions to access instruction and data memory. The physical separation is realized with two separate memories, the access is through one own bus.

Motivation

The advantage of this architecture consists in that commands and data are loaded at the same time, or can be written. In a classical von Neumann architecture of at least two consecutive bus cycles are necessary for this purpose.

In addition, the physical separation of data and program ensures that access rights separation and memory protection are easy to implement. In order to prevent, for example, that software problems with program code can be overwritten, a read-only memory is in use for the program code ( eg, ROM, punch cards ) used for data write and readable memory (eg RAM, ring core memory ). A disadvantage, however, that unneeded data storage can not be used as program memory, so an increased memory fragmentation occurs.

History

The Harvard architecture was first implemented mainly consistent in RISC processors. Modern processors Harvard architecture are able to fill a plurality of parallel arithmetic logic units at the same time with data and commands. In signal processors C6x family from Texas Instruments this is possible, for example, for up to eight processing plants.

Another advantage of the separation is that the data word width ( the smallest addressable unit ) and the instruction word width can be set independently. This can also, if required, the efficiency of the program memory footprint can be improved because it is not directly dependent on the data bus, but only on the command set. This may be in embedded systems or small microcontroller systems of interest, for example.

Single-chip microcontroller that work with solid programs that use most of the Harvard architecture. Known representatives are eg ( PICmicro ) from Microchip Technology Inc., the Intel 8048 and 8051 families and the AVR series from Atmel.

A major expansion of the Harvard architecture was made by the American company Analog Devices in the early 1990s with the introduction of super Harvard architecture technology, in which said memory segments are designed as dual-port RAMs that cross between program - and data buses are.

Many modern processors use a hybrid of Harvard and von Neumann architecture in which data and program are from each managed separately within the processor chips have their own caches and MMUs and run over separate internal buses, external but lie in a common memory. When CPU pipelining is implemented, the advantage of this form is mixed ( at the CPU level ), that the individual pipeline stages may be separated with respect to memory accesses. A typical example of this type is the Motorola 68030 processor, which was developed in the 1980s.

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