IBM Power

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The IBM Power architecture ( a backronym for performance optimized with enhanced RISC) is the granddaddy and the mainframe branch of the PowerPC CPU from IBM. It comes ( to POWER4 ) in the iSeries, formerly AS/400, pSeries, RS/6000 formerly, and now with Power5 processors in the systems IBM eServer p5 and eServer i5 used.

POWER

From the original Power family of the first single-chip processor PowerPC 601 was modified, which emerged ( AIM alliance ) from the merger of Apple, IBM and Motorola. The Power Architecture quickly found in the areas of the workstation computers (Apple), in embedded systems as well as in space use.

POWER2

From the 1993's eight- chip processor POWER2 the POWER2 SC, the first power processor in 1996 from a chip, derived, and still sold until 1999.

POWER3

Published in 1998 and the POWER3 POWER3 II with 64-bit CMOS6S2 technology, and 225 mm ² ( POWER3 ) and 170 mm ² ( POWER3 II) the surface.

POWER4

The IBM p690, called Regatta, realized for the first time on a chip two CPU cores (initially from 2001 POWER4, 180 nm, 1.1-1.3 GHz), a shared L2 cache and a very fast switch interface. But the connection interface of these chips were novel. So that four processor cores are connected to a common multi-chip module (MCM ); IBM, reaching an extremely high packing density of eight CPUs in an area of ​​90 cm ². The regatta reached with 32 POWER4 CPUs (from 2002: 130 nm, 1.2-1.9 GHz, 267 mm ², 185 million transistors) in March 2004, a peak power of over 1 million points in the database benchmark tpm -C.

From the POWER4 developed by IBM PowerPC 970 came out, which was referred to by Apple as G5. He is considered the successor to the PowerPC G4, who came from Motorola.

Power5

Power5 130 nm 1.5; 1.65; 1.9 GHz dual- core processor, 389 mm ², 276m Transisitoren, with simultaneous multithreading (SMT ) and integrated memory controller. Cache: 64k2w - lru ( instructions ) and 32k4w - lru (data). L2 cache 1.92m10w - lru. in partitionable pSeries and iSeries SMP servers from 1 to 64 CPUs, 1 GB main memory and 2 TB 5-240 PCI-X lots. A multi-chip modules with four CPU chips (ie eight cores ) and four 36 MB L3 cache chips consists of 89 metal layers with a total of 5370 I / O pins, of which 2 313 signal pins are and 3057 needed for energy supply are.

Power5 of 2004, the development of POWER4. In addition to the POWER4 architecture is located on the chip, the L3 directory and the memory controller, this is a higher overclocking. Power5 is three times more powerful than POWER4 up to. IBM claimed that this is for the best time server scalability (linear to 64 -way ) all offered on the market provided. Another unique feature offers the Power5 architecture with the Advanced Power Virtualization ( APV), among others, the ability to split the physical CPUs in virtual CPUs then again between the different logical partitions (LPARs ) are distributed dynamically and automatically during operation. APV is sold since 21 December 2008 under the name PowerVM.

On 4 October 2005, IBM announced the Power5 90 nm dual-core processor with 1.5 or 1.9 GHz. As of mid- 2006, there were single-and dual -core Power5 processors up to 2.3 GHz.

Power6

The Power6 processor was manufactured from 2007 in the 65 - nm process and has a die area of 341 mm ². On this surface are about 790 million transistors. Most of the area is occupied by 8 MiB comprehensive L2 cache, of which each core half, ie 4 MiB, be allocated. The size of the L1 caches 128 KiB, divided into 64 KiB data and instruction cache 64 KiB. The external L3 cache in the size of 32 MiB can be addressed with a range of 80 GiB / s. The Power6 processors with 4.2; 4.7 and 5.0 GHz clock frequency available.

IBM sees this processor range from enterprise databases (eg, IBM System p and IBM System i ) and high-performance computers, as they are required in aircraft and accident simulations in the automotive industry.

Power7

The Power7 has come on the market in 2010 and consists of up to eight cores, each core can execute in parallel up to four threads. The CPU is manufactured in 45 nm and the maximum clock frequency is 4.1 GHz.

Currently, the Power7 CPU which is manufactured in 32nm and now reaches a maximum clock speed of 4.42 GHz.

Power 8

On the Hot Chips 25 conference, IBM has introduced the Power 8 CPU with 12 cores. Each of the 12 cores that can access each 512KB L2 cache and 96MB L3 cache and total to 128MB L4 cache is run able means of simultaneous multithreading 8 threads simultaneously. The Power 8 is manufactured in 22nm process and has an area of ​​650 mm ² THE. About a connected 32-channel memory controller can be connected 1TB of DDR3 -1600 RAM. No clock frequencies have yet been announced.

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