Intel 80386

  • Intel
  • AMD
  • IBM

The 80386 ( early term iAPX 386 ) is an x86 CPU, which was developed by Intel under the brand name i386 as successor to the 80286 and produced from 1985 to September 2007. The 386 - like the 80386 is often called (voiced Dreisechsundachtziger ) - was later copied by AMD and sold as Am386, while Chips & Technologies developed a compatible own version. IBM licensed the i386SX paintings and developed the improved IBM 386SLC.

  • 3.1 POPA / POPAD bug
  • 3.2 Review of the limit of the TSS
  • 4.1 i386DX
  • 4.2 i386SX
  • 4.3 i386SL
  • 4.4 RapidCAD -1
  • 4.5 RapidCAD -2
  • 4.6 I376
  • 4.7 i386EX, i386EXTB and i386EXTC
  • 4.8 i386CXSA and i386SXSA (also known as i386SXTA )
  • 4.9 i386CXSB

Historical significance

With the 80386, Intel took the change to 32 -bit architecture (IA -32, often also called i386), whose functions i7 also in all subsequent models to the Core (2012 ) are still present and at the same time other manufacturers as a template for own processors served. Registers this processor family as well as the address space of the architecture are 32 bits wide. Even today, the 80386 for control tasks ( eg, telephone switching systems ) and in space will be used.

The development at Intel launched from 1982 John Crawford.

Architecture

Variants

There were a total of four variants of this CPU, which differed in the bus and in the application. The production of i386EX as an embedded version of i386SX was stopped in 2007.

Intel386SX

A variant of the 80386 is the 80386SX. He has only a 16-bit external data bus and a 24 -bit wide address bus, reserves internally but with the 32 -bit microarchitecture of 80386. The 24 -bit wide address bus limits the addressable physical memory of the 386SX, although at 16 MiB; in view of a conventional beginning of the 1990s in the home memory capacity, usually of a maximum of 4 MiB but that was not a serious limitation, since many 386SX Motherboard a memory configuration of 16 MiB also not allowed. From a programming perspective, there is practically apart from the memory limitation is no difference between the 386SX and the "real" 80386, which was renamed to distinguish it from his little brother after its introduction in 80386DX. Due to the reduced data bus width and lower clock frequencies available the 386SX achieved compared to the 386DX only a significantly lower execution speed.

Intel386SL

The Intel386SL is a version of i386SX for portable computers. With it, the System Management Mode (SMM ) has been introduced, which can set to power saving purposes, the CPU into a deep sleep.

RapidCAD

The RapidCAD was based on 486 technology upgrade for 386 systems. The RapidCAD consisted of two chips, the RapidCad1 and the RapidCad2, the former replaced the 80386 CPU, and the latter the 80387 coprocessor. The RapidCad2 but not containing the electronics of the co-processor, but only a logic to generate external bus signals. The actual coprocessor was already integrated in RapidCad1.

Compared to an i386 system with I387 coprocessor brought the RapidCAD - depending on the application - a moderate performance increase of about 30 percent; to a system with 80486 but handed the power not approach. Besides the high price, among other things this circumstance made ​​sure that the RapidCAD experienced no widespread use, and the two chips are coveted collector's items today.

Segments

The 80386 can directly up to 4 GiB main memory address ( 386SX: 16 MiB). The logical address space is 246 bytes = 64 TiB, which is only theoretically completely usable. The processor uses it in protected mode, the segmented memory addressing with 16 -bit-wide selectors and - depending on the operating mode - 16 or 32 -bit offsets.

The segmentation unit supports four privilege levels that are intended for the following tasks:

  • Ring 0 - for the kernel and device drivers
  • Ring 1 - for drivers who do not need unlimited access hardware ( for example, file system drivers ), rarely used
  • Ring 2 - for System Services
  • Ring 3 - for the execution of normal applications

Few PC operating systems have utilized these four privilege levels. Most (also due to the compatibility with other processor architectures, which have only two privilege levels ) only ring 0 ( kernel ) and ring 3 is used ( for all other code).

Regarding safety, the Protected Mode significantly superior to the flat Adressiermodell which has now prevailed. However, use almost all newer operating systems for application programs exclusively the "Flat Memory " model. This simplifies programming and is transferable to other processor architectures that do not have segmentation unit.

On the hardware side is also possible the parallel use of segmentation and paging. It will only calculate the linear address by segmenting and then converted via the paging in the physical address. Without paging corresponds to the linear address to the physical address.

When using a so-called "Flat Memory " model, are displayed in the data, code and stack segment in a linear 4 GiB address space of the application programs, the memory within the application programs using simple 32- bit offset is addressable. Thus, the memory protection provided by the segmentation unit, undermined. In introduced by AMD x64 mode, the newer 64 -bit processors, not an extension of segmentation was provided, so that only a "flat memory model " is available.

The paging unit allows for a relatively simple page-based memory protection. Meanwhile, an attempt is made to connected to the " Flat Memory " model vulnerabilities caused by new hardware extensions such as NX bit get at (from AMD Athlon 64) or SMEP.

Paging

To manage an additional layer, which uses 4 KiB large memory pages ( engl. memory pages ) is now used. The base addresses of all pages are listed in Tables page (English page tables ). These are stored in directories page (English page directories ) to 1024 entries. An address space of size 4 GiB is thus divided into 1024 × 1024 pages of 4 KiB. Thus, the linear 32-bit address is divided into three components:

At the page level, there are two privilege levels:

  • Supervisor mode - for operating system and driver ( ring 0, 1 and 2)
  • User-Mode - for application programs (Ring 3 )

In brackets are the equivalent of the segment is given privileges.

Register

He has eight 32- bit general registers, although some have specific uses in connection with various commands, but otherwise free for general computing and data exchange can be used:

In addition, there are also other registers to control the behavior of the CPU:

( It can be in the GDT real time several LDT entries are )

( Lower 16 bits of CR0 are the MSW from 80286 assumed)

( There may be several at the same time TR in the GDT and LDT are )

All general-purpose register, and the EIP and EFLAGS are at 32 bit extended ( e comes from the English extended) versions corresponding 16- bit registers of the previous 8086-80286.

Processor bugs

POPA / POPAD bug

This error occurs in all 386ern. This error occurs if immediately after the POPA or POPAD command followed by a command in which a memory address is calculated from a base and index registers. Consequence of this error is that the value in the EAX register is undefined. If used as a base or index register in memory access EAX, then the processor will hang (only POPA ). The Linux kernel performs at boot time by a test and is at present the error message Checking for popad bug ... buggy. from, but then boots on.

Revision of the level of TSS

The processor checks whether the entered size of the TSS is large enough. 10 The exception is triggered when the TSS is less than 101 bytes, but should actually trigger even at less than 103 bytes.

Model data

I386DX

  • L1 cache: No
  • L2 cache: the mainboard dependent
  • Design: PGA PQFP or 132- pin
  • Operation voltage ( Vcore ): 5 V
  • Release Date: October 17, 1985
  • Manufacturing Technology: Getting types CHMOS III 1.5 microns, later CHMOS IV with 1.0 micron
  • The size: 104 mm ² ( 10 mm x 10 mm, CHMOS III) and 39 mm ² ( 6 mm x 6.5 mm, CHMOS IV)
  • Transistor Count: 275,000
  • Clock rates: 12 MHz ( the first models of the i386)
  • 16 MHz
  • 20 MHz
  • 25 MHz
  • 33 MHz

I386SX

  • L1 cache: No
  • L2 cache: No
  • Type: 100-pin PQFP, PGA with 88 pins
  • Operation voltage ( Vcore ): 5 V
  • Release Date: June 16, 1988
  • Manufacturing Technology: CHMOS IV, 1.0 micron
  • The size: 104 mm ² with 275,000 transistors
  • Clock rates: 16 MHz
  • 20 MHz
  • 25 MHz
  • 33 MHz

I386SL

Version of i386SX for portable computers. With it, the System Management Mode (SMM ) has been introduced, which can set to power saving purposes, the CPU into a deep sleep.

  • L1 cache: No
  • L2 cache: 16 to 64 KiB possible
  • Design: PGA with? Pins, PQFP with 132 pins
  • Operation voltage ( Vcore ): 5 V
  • Release Date: October 15, 1990
  • Manufacturing Technology: 1.0 micron
  • The size? mm ² with 855,000 transistors
  • Clock rates: 20 MHz
  • 25 MHz

RapidCAD -1

  • Number of transistors: 800,000
  • Manufacturing Process: 0.8 micron
  • Cache: on-board, no on-die cache
  • Architecture: 80486 technology with 80386 instruction set and pinout
  • Coprocessor: Integrated
  • Case: 132 pin PGA
  • Power Consumption: 3.5 Watt
  • Clock speeds: 25 and 33 MHz

RapidCAD -2

The RapidCAD -2 is a PLA for generating the signal FERR.

  • Introduced: 1992
  • Number of transistors: 275,000
  • Manufacturing Process: 0.8 micron
  • Housing: 68 Pin, PGA ( for 387er - base)
  • Clock speeds: 25 and 33 MHz

I376

The I376 is an embedded processor based on the i386SX and can be considered as the predecessor of i386EX. It does not support real mode and no paging.

  • Data bus: 16 bits
  • Address bus: 24 bit
  • L1 cache: No
  • L2 cache: No
  • Type: 100-pin PQFP and PGA -88
  • Operation voltage ( Vcore ): 5 V
  • Release Date: January 16, 1989
  • Cessation of production: June 15, 2001
  • Manufacturing Technology: CHMOS IV, 1.0 micron
  • The size?
  • Compatible FPU: 80387SX
  • Special features: boot in protected mode ( does not support real mode )
  • Clock rates: 16 MHz
  • 20 MHz

I386EX, i386EXTB and i386EXTC

Embedded version of i386SX with system and power management.

  • Two interrupt controller 82C59A
  • Timers, counters ( three channels)
  • Asynchronous SIO (two channels )
  • Synchronous SIO (one channel )
  • Watchdog timer ( hardware / software)
  • PIO
  • Data bus: 16 bits
  • Address bus: 26 bit
  • L1 cache: No
  • L2 cache: No
  • External FPU: i387SX or i387SL
  • Design: PQFP 132- pin, 144-pin SQFP and PGA with 168 pins
  • Operation voltage ( Vcore ): 2.7 V to 5.5 V
  • Release Date: 1994
  • Manufacturing Technology: 0.8 micron
  • The size? mm ² at? transistors
  • Clock rates: 16 MHz - i386EX, 2.7 V to 3.3 V
  • 20 MHz - i386EX at 3.0 V to 3.6 V
  • 25 MHz - i386EX, at 4.5 V to 5.5 V
  • 20 MHz - i386EXTB, 2.7 V to 3.6 V
  • 25 MHz - i386EXTB at 3.0 V to 3.6 V
  • 25 MHz - i386EXTC, at 4.5 V to 5.5 V
  • 33 MHz - i386EXTC, at 4.5 V to 5.5 V

I386CXSA and i386SXSA (also known as i386SXTA )

Embedded CPU with transparent power management mode, integrated MMU and TTL compatible inputs (only SXSA version).

  • Data bus: 16 bits
  • Address bus: 26 bit (24 bit in i386SXSA )
  • L1 cache: No
  • L2 cache: No
  • External FPU: i387SX or i387SL
  • Type: 100-pin PQFP
  • Operation voltage ( Vcore ): 4.5 V to 5.5 V ( 25 and 33 MHz)
  • 4.75 V to 5.25 V (40 MHz)
  • 25 MHz
  • 33 MHz
  • 40 MHz

I386CXSB

Embedded CPU with transparent power management mode and integrated MMU.

  • Data bus: 16 bits
  • Address bus: 26 bit
  • L1 cache: No
  • L2 cache: No
  • External FPU: i387SX or i387SL
  • Type: 100-pin PQFP
  • Operation voltage ( Vcore ): 3.0 V at 16 MHz
  • 3.3 V at 25 MHz

Other manufacturers

  • Am386DX
  • Am386SX
  • 38600SX
  • 38605SX
  • 38600DX
  • 38605DX
  • 386SLC

Pictures of Intel 80386

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