Intel MCS-51
- Intel
- Philips Semiconductors
- NEC
- Siemens AG
MCS 51 is the name of a 1980 presented by Intel family of 8 -bit microcontrollers. The MCS-51 family succeeds the MCS-48 family. At the beginning they had only three members with the designations 8051, 8031 and 8751 In 8031, the application is in an external module, whereas there is the application program in the block itself, the 8051 and 8751 -. Either in a mask-programmed ROM ( 8051 ) or in an EPROM ( 8751 ). In 1983, the corresponding versions 8052, 8032 and 8752 were presented, each with dual ROM as RAM and an additional timer. The family was initially then manufactured in NMOS technology, after several years even in today's conventional CMOS technology.
Intel has licensed the MCS-51 CPU core to many semiconductor manufacturers, thus creating the basis for a cross-vendor industry standard. For a long MCS-51 compatible microcontroller not only from Intel, but also from Analog Devices, Atmel, Infineon, Maxim / Dallas, Oki, NXP Semiconductors ( Philips), Silicon Laboratories, Texas Instruments and are made a v..
From the Intel SDK -51 as a development system has been offered.
Structure
The MCS-51 family has produced very many members, including the Siemens 80C517. They have the following in common:
- 8- bit processor core with a uniform command set
- At least 128 bytes of internal RAM
- External RAM and ROM
- A uniform addressing model for so-called Special Function Register (SFR )
- Full - duplex UART
- 5 interrupt sources
- 2 interrupt priorities
- Various timer
Due to the different instruction lengths ranging from one to three bytes and the different execution times for a command, it is clearly a CISC architecture.
One instruction cycle corresponds to the originally developed by Intel structure one to three machine cycles ( multiplication and division require 4 ). A machine cycle is equivalent to 12 clock cycles. Today ordinary modifications of the MCS -51, however, are usually fixed with only two clock cycles per machine cycle. Thus, a significantly higher command processing is possible at the same clock frequency.
A special feature of this processor is the bit processor, which allows quick and easy bit manipulation bit-addressable area.
Due to the wide distribution of this family of processors and the associated large software libraries there are also a variety of synthesizable MCS -51 implementations. These are the so-called IP cores free in a hardware description language such as VHDL and code is available. They are suitable for use in FPGAs and Application Specific Integrated Circuits ( ASICs). Typical application examples are USB controllers, as they are used in a printer or interface adapters. In this MCS-51 microcontroller are integrated to control the various protocols.
Variants
The MCS-51 series includes the following known microcontroller ( all memory data is in bytes):
In addition, there are various companies extended MCS-51 microcontroller, such as Siemens (now Infineon) developed and manufactured in NMOS technology:
The CMOS versions of the Siemens MCS -51 series are functionally identical, but not in all versions pin-compatible.
More modern MCS-51 compatible microcontroller, which are produced in CMOS technology with flash memory and have often providing faster command processing, more memory or special interfaces:
Memory organization
In its original form it is a Harvard architecture, but many newer MCS-51 development boards have a modified Harvard architecture. With this architecture, a part of the XRAMs ( Extended Data RAM) is reflected by means of an address decoder in the program memory. This allows a running mostly from ROM terminal software eg via Serial Interface to load software coming into the program memory and run after the transfer.
The stack is always definable in the internal RAM. The byte order is Little Endian first.
Special Function Register White: 8051 Blue: in addition in 8052
Interrupt addresses
Data storage
The four register banks each containing 8 registers that are addressable as either register or her address. Advantages of the register in the " RAM for general use " are the shorter commands. Registers 0 and 1 can be used as 8 -bit data pointer in the internal and external RAM. Through clever use of register banks, the response time to an interrupt can be shortened, because the data does not need to be moved in the stack.
Since the upper RAM and the special function registers share the addresses, the type of addressing is used to distinguish. The upper RAM can only indirectly by means of register 0 and register 1 to address, while the special function registers are accessible by direct addressing.
When programming the extended RAM ( engl. extended data RAM or short XRAM ) is distinguished from normal RAM by the command. MOV speaks to the internal RAM, while MOVX addresses the XRAM. However, the XRAM is indirectly addressed, but linear. With the early versions XRAM was always externally with newer versions, it may be partially or fully integrated.
Based on the address bus width of 16 bits XRAM are possible up to 65536 bytes.
The special function registers or memory addresses of the XRAMs be used by certain types of controllers and controller boards for extensions of all kinds. As an example:
- Other inputs and outputs
- 16- bit arithmetic logic unit
- USB controller
- ...
Especially with the synthesizable MCS-51 implementations, offers this because the instruction set of the MCS-51 family is not changed, thus maintaining compatibility to their development tools.
Program memory
Since the address bus is 16 bits wide, the external program memory can be up to 65536 bytes. It can be used either internal or external program memory. A simultaneous operation is not possible.
MOVC means the program can read from the program memory, which is useful in the implementation of tables.
Ports
Port 1 and port 3 of the microcontroller are N- channel MOSFETs, with internal pull -up.
Read RMW commands the value from memory, while all other commands fetch the values from the pin.