List of AMD Opteron microprocessors

Opteron is the brand name of the server and workstation processors from AMD.

All Opteron for Socket 939 and 940 have a three -digit model number Opteron XYY. All newer Opteron have a four-digit model number Opteron XZYY. In the previous numbering scheme the first digit X specifies how many processors of the processor on the motherboard can be used:

The second number Z of the four-digit model number stands for the generation of Opteron processors:

  • First-generation Opteron (Socket 939 and 940) do not have this marking
  • 2 - the second generation Opteron (Socket AM2 and F)
  • 3 - Third Generation Opteron (Socket AM2 and F / F )
  • 4 - the fourth generation Opteron (Socket AM2 and F / F )

With the new Lisbon-/Magny-Cours-Prozessoren AMD introduced in 2010 along with new sockets and a modified four-digit numbering scheme before: X is now available for the platform and Z for the generation of new models.

The last two digits YY in all numbering schemes encode the clock of the processor. Overall there is a larger number here at a higher speed. Within a generation, and with the same number of processor cores, the information is comparable.

  • The additional designations HE and EE have models with lower and lower power dissipation.
  • The additional designation SE has models with higher power consumption, it usually affects the highest clocked models of a generation.
  • 2.1 Denmark, Italy and Egypt 2.1.1 Denmark ( 1yy )
  • 2.1.2 Italy ( 2YY )
  • 2.1.3 Egypt ( 8yy )
  • 3.1 Santa Ana and Santa Rosa 3.1.1 Santa Ana ( 12yy )
  • 3.1.2 Santa Rosa ( 22yy )
  • 3.1.3 Santa Rosa ( 82yy )
  • 4.1 Budapest and Barcelona 4.1.1 Budapest ( 13yy )
  • 4.1.2 Barcelona ( 23yy )
  • 4.1.3 Barcelona ( 83yy )
  • 4.2.1 Suzuka ( 13yy )
  • 4.2.2 Shanghai ( 23yy )
  • 4.2.3 Shanghai ( 83yy )
  • 5.1 Istanbul 5.1.1 Istanbul ( 24yy )
  • 5.1.2 Istanbul ( 84yy )
  • 6.1 Lisbon ( 41yy )
  • 6.2 Magny -Cours ( 61yy )
  • 7.2 Valencia ( 42yy )
  • 7.3 Interlagos ( 62yy )
  • 7.4 Abu Dhabi ( 63yy )
  • 8.1 Kyoto

First-generation Opteron ( single-core )

Sledgehammer

  • Revision: B3, C0, CG
  • L1 - Cache: 64 64 KB ( data instructions ), 2- way set-associative
  • L2 cache: 1024K processor with clock, 16 - way set associative
  • All models support MMX, Extended 3DNow!, SSE, SSE2, NX bit, AMD64 SMP and
  • Integrated North Bridge with controller memory: Runs with processor clock
  • Storage support: Registered DDR SDRAM to PC - 3200R (B3: up PC 2700R )
  • Manufacturing Technology: 130 nm ( SOI)
  • The size: 193 mm ² at 105.9 million transistors

Sledgehammer ( 1yy )

  • For systems with a processor

Sledgehammer ( 2YY )

  • For systems with up to two processors

Sledgehammer ( 8yy )

  • For systems with up to eight processors

Venus, Troy and Athens

  • Revision: D4, E4, E6
  • L1 - Cache: 64 64 KB ( data instructions ), 2- way set-associative
  • L2 cache: 1024K processor with clock, 16 - way set associative
  • All models support MMX, Extended 3DNow!, SSE, SSE2, SSE3 (except Rev D4), NX bit, SMP, AMD64, and OPM
  • Integrated North Bridge with controller memory: Runs with processor clock
  • Memory Support: DDR - SDRAM PC -3200 to (Socket 939), Registered DDR SDRAM to PC - 3200R (Socket 940)
  • Manufacturing Technology: 90 nm ( SOI)
  • The size: 115 mm ² at 114 million transistors
  • The size: 199 mm ² at 233.2 million transistors (only revision E6, part number / OPN ends with CF)

Venus ( 1yy )

  • For systems with a processor

Troy ( 2YY )

  • For systems with up to two processors

Athens ( 8yy )

  • System for up to eight processors

First-generation Opteron ( Dual-Core)

Denmark, Italy and Egypt

Dual-core processor

  • Revision: E1, E6
  • L1 - Cache: 64 64 KB per core (data instructions ), 2- way set-associative
  • L2 cache: 1024K per core processor with clock, 16 - way set associative
  • All models support MMX, Extended 3DNow!, SSE, SSE2, SSE3, NX bit, SMP, AMD64, and OPM
  • Integrated North Bridge with controller memory: Runs with processor clock
  • Memory Support: DDR - SDRAM PC -3200 to (Socket 939), Registered DDR SDRAM to PC - 3200R (Socket 940)
  • Manufacturing Technology: 90 nm ( SOI)
  • The size: 199 mm ² at 233.2 million transistors

Denmark ( 1yy )

  • For systems with a processor

Italy ( 2YY )

  • For systems with up to two processors

Egypt ( 8yy )

  • For systems with up to eight processors

Second-generation Opteron ( Dual-Core)

Santa Ana and Santa Rosa

Dual-core processor

  • Revision: F2, F3
  • L1 - Cache: 64 64 KB per core (data instructions ), 2- way set-associative
  • L2 cache: 1024K per core processor with clock, 16 - way set associative
  • All models support MMX, Extended 3DNow!, SSE, SSE2, SSE3, NX bit, SMP, AMD64, OPM and AMD-V
  • Integrated North Bridge with controller memory: Runs with processor clock
  • Memory support: DDR2 SDRAM up to PC2 -6400 (Socket AM2 ), Registered DDR2 SDRAM up to PC2- 5300R (Socket F)
  • Manufacturing Technology: 90 nm ( SOI)
  • The size: 230 mm ² at 227.4 million transistors

Santa Ana ( 12yy )

  • For systems with a processor

Santa Rosa ( 22yy )

  • For systems with up to two processors

Santa Rosa ( 82yy )

  • For systems with up to eight processors

Third-generation Opteron (Quad -Core)

Budapest and Barcelona

Quad-core processor ( quad-core )

  • Revision B1, B2, BA, B3
  • L1 - Cache: 64 64 KB per core (data instructions ), 2- way set-associative
  • L2 cache: 512 KB per core with processor clock, 16 - way set associative
  • L3 Cache: 2,048 KB with Northbridge clock, 32 - way set associative
  • MMX, Extended 3DNow!, SSE, SSE2, SSE3, SSE4a, AMD64, OPM, NX bit, SMP and AMD-V
  • Integrated North Bridge with controller memory: 1.6 GHz to 2.0 GHz
  • Memory support: DDR2 SDRAM up to PC2 -6400 (Socket AM2 ), Registered DDR2 SDRAM up to PC2- 5300R (Socket F)
  • Manufacturing Technology: 65 nm ( SOI)
  • The size: 285 mm ² at 463 million transistors

Budapest ( 13yy )

  • For systems with a processor

Barcelona ( 23yy )

  • For systems with up to two processors

Barcelona ( 83yy )

  • For systems with up to eight processors

Suzuka and Shanghai

Quad-core processor ( quad-core )

  • Revision: C2
  • L1 - Cache: 64 64 KB per core (data instructions ), 2- way set-associative
  • L2 cache: 512 KB per core with processor clock, 16 - way set associative
  • L3 Cache: 6,144 KB with Northbridge clock, 48 - way set associative
  • MMX, Extended 3DNow!, SSE, SSE2, SSE3, SSE4a, AMD64, OPM, NX bit, SMP and AMD-V
  • Integrated Northbridge memory controller Socket F: 2.0 GHz ( up to model number X380 ), 2.2 GHz (from X382 )
  • Integrated North Bridge with controller memory socket AM3: 2.2 GHz
  • Memory support: DDR2 SDRAM up to Registered PC2- 6400R (Socket F), DDR3 SDRAM up to PC3 -8500 (Socket AM3)
  • Manufacturing Technology: 45 nm ( SOI)
  • The size: 258 mm ² at 758 million transistors

Suzuka ( 13yy )

  • For systems with a processor

Shanghai ( 23yy )

  • For systems with up to two processors

Shanghai ( 83yy )

  • For systems with up to eight processors

The fourth generation Opteron ( Hexa -core )

Istanbul

Six Core Processor ( Hexa -core )

  • Revision: D0
  • L1 - Cache: 64 64 KB per core (data instructions )
  • L2 cache: 512 KB per core with processor clock
  • L3 Cache: 6,144 KB with Northbridge clock
  • MMX, Extended 3DNow!, SSE, SSE2, SSE3, SSE4a, AMD64, OPM, NX bit, SMP and AMD-V
  • Integrated Northbridge memory controller: 2.2GHz
  • Memory support: DDR2 SDRAM up to Registered PC2- 6400R (Socket F)
  • Manufacturing Technology: 45 nm ( SOI)
  • The size: 346 mm ² at 904 million transistors

Istanbul ( 24yy )

  • For systems with up to two processors

Istanbul ( 84yy )

  • For systems with up to eight processors

The fifth generation Opteron (Quad- or hexa- or octo- or dodeca -core )

Lisbon ( 41yy )

Native six-core processor Istanbul for new socket ( Hexa -core ), individual models with only four active cores ( quad-core ).

  • Revisions: D0, D1
  • L1 - Cache: 64 64 KB per core (data instructions )
  • L2 cache: 512 KB per core with processor clock
  • L3 cache: 6 MB with Northbridge clock ( with active snoop filter ( HT Assist ) only 5 MB available )
  • MMX, Extended 3DNow!, SSE, SSE2, SSE3, SSE4a, AMD64, NX bit, SMP, OPM and AMD-V
  • Memory support: DDR3 SDRAM up to PC3- 10667, two memory channels per processor socket

Magny -Cours ( 61yy )

Twelve -core processor ( dodeca -core ), individual models with only eight active cores ( Octo -Core).

  • Two native six-core processors Lisbon on a multi -chip module, four memory channels per processor socket.

The sixth generation Opteron ( Bulldozer -based)

A single The AM3 , variants with only two activated with four Bulldozer modules in the base modules

  • Revision: B2
  • L1 cache: 64 KB for instructions for each module ( shared between 2 cores ), the core 16 KB for data
  • L2 cache: 2048 KB per module with processor clock ( shared between 2 cores )
  • L3 Cache: 4 MB or 8 MB with Northbridge clock
  • Memory support: DDR3 SDRAM up to PC3- 12800 (two DIMMs) or PC3- 14900 ( one DIMM per channel), two memory channels
  • HyperTransport ports with 5.2 GT / s (2600 MHz)

Valencia ( 42yy )

The a single with four Bulldozer modules in the base C32, individual variants with only three active modules

  • Revision: B2
  • L1 cache: 64 KB for instructions for each module ( shared between 2 cores ), the core 16 KB for data
  • L2 cache: 2048 KB per module with processor clock ( shared between 2 cores )
  • L3 Cache: 8 MB ​​with Northbridge clock
  • Memory support: DDR3 SDRAM up to PC3- 12800, two memory channels per processor socket
  • HyperTransport ports with 6.4 GT / s

Interlagos ( 62yy )

Two Valencia - This on a multi-chip module into the socket G34, four memory channels per processor socket variants with 4 to 16 cores

  • Revision: B2
  • L1 cache: 64 KB for instructions for each module ( shared between 2 cores ), the core 16 KB for data
  • L2 cache: 2048 KB per module with processor clock ( shared between 2 cores )
  • L3 cache: 2 MB * ​​8 with Northbridge clock
  • Memory support: DDR3 SDRAM up to PC3- 12800, four memory channels per processor socket
  • HyperTransport ports with 6.4 GT / s

Abu Dhabi ( 63yy )

Two die on a multi-chip module into the socket G34, four memory channels per processor socket variants with 4 to 16 cores

  • Revision: C0 ( Piledriver core )
  • L1 cache: 64 KB for instructions for each module ( shared between 2 cores ), the core 16 KB for data
  • L2 cache: 2048 KB per module with processor clock ( shared between 2 cores )
  • L3 cache: 2 MB * ​​8 with Northbridge clock
  • New Piledriver Features: FMA3, BMI1, TBM, F16C
  • Memory support: DDR3 SDRAM up to PC3- 12800, four memory channels per processor socket
  • HyperTransport ports with 6.4 GT / s

Opteron SOC on APU - based with a low TDP

Kyoto

The a single with four Jaguar cores as SOC

  • L1 cache: 32 KB per core for instructions and 32 KB for data
  • L2 cache: 2048 KB, shared by all cores
  • Memory support: DDR3 SDRAM with ECC up to PC3- 12800 (two DIMMs), one memory channel
  • 8 PCIe lanes 2
  • 2 SATA 2/3-Ports
  • 8 USB 2.0 ports, 2 USB 3.0 ports
  • The maximum TDP can be configured by the customer.

Notes

  • AMD processor
  • List (processors )
X86-64 DDR-SDRAM Byte Northbridge (computing) Average CPU Power Bulldozer (microarchitecture) SSSE3 AES instruction set XOP
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