Load-Link/Store-Conditional

Link Load / Store Conditional ( LL / SC) (English about " reference load / conditionally writing ") is a pair of processor instructions that implement a read-modify -write operation. LL command loads a memory location, their contents may be changed, and the SC command to write the new value back to the referenced memory location, under the condition that it has not changed., The memory location modified write operation fails. For the degree of change, there is a strong and a weak semantics (see below).

LL / SC operations are used to implement atomic operations without the use of locks (lock - free ). By linking reading and writing operation semantics and is more restrictive than the compare -and -swap operation, because they do not ( non- changing ) can detect access to the referenced memory location.

Implementations of LL / SC instruction pair exist on different computer architectures, including: LDL_L / stl_c and LDQ_L / stq_c ( Alpha processor ), lwarx / stwcx ( PowerPC), ll / sc ( MIPS architecture ), and LDREX / strex ( ARM architecture version 6 ). These architectures are usually based on the RISC philosophy, whose instruction set reduces the memory accesses to read and write commands.

Strong and weak semantics

In the narrow interpretation of the semantics of LL / SC instruction pair fails only if takes place, access to the referenced memory location between the LL and the SC command.

However, on many architectures other events lead to unnecessary failure, for example, context switches, interrupts, or other memory accesses.