Low Voltage Differential Signaling

In the English term Low Voltage Differential Signaling (LVDS) is an interface standard for high -speed data transmission. LVDS is standardized according ANSI/TIA/EIA-644-1995. It describes the physical layer, not the higher protocol layers based on it. Important features are:

  • Differential voltage level
  • Relatively low voltage level ( engl. low voltage)
  • The signals are generated with a constant current source

Voltage level

Low voltage (low voltage) is that instead of a conventional high ( high voltage ) voltage for digital systems of 5 V or 3.3 V, a lower voltage is used. This has several advantages. With classical interfaces, such as EIA-422, a relatively high power is required to change the charge of the cable. The voltage variations occurring (high dV / dt) and the high-frequency charging and discharging (high di / dt) are associated with high-frequency electric (E ) field and magnetic field (H-field ) that generate strong electromagnetic interference. The high-frequency Umladungsströme also ensure the power supply lines for problems. The ever more structural miniaturization of modern semiconductors also brings a reduction of the supply voltages with them. At high data rates, therefore, one can not avoid a reduction in signal level. LVDS operates with a voltage swing of 0.3 V differential signal transmission is that two lines are used and the difference of the voltages for the logic state is critical. When the difference LVDS 0.3 V, while the absolute voltage to GND is about 1.2V. A logic transition is generated by opposite changes in the voltage on both lines. This is referred to as a balanced signal transmission. The changes in the signal level on the individual conductors always have opposite signs.

Principle of operation

On the driver side, a constant current source generates a current of 3.5 mA. This is dependent on the logic level of the input signal is switched between the two signal lines. In this case, the other line is connected to the zero level. On the receiver side, the current flows through a terminating resistor of 100 Ω. This value corresponds to the line impedance, thereby to prevent reflections on the line. The signal current generated in the receiver, a change in voltage of 350 mV to -350 mV, and vice versa.

Layout ( PCB tracks )

The effect of the low voltage level that LVDS signals are sensitive to electromagnetic interference. A suitable layout can counteract the noise sensitivity.

It is recommended to return conductors close together to lead, or to make a conductor over a ground plane such that adjusts by the geometry and the dielectric of the PCB of the line impedance. Due to the low surface which span the closely spaced out head, even a less magnetic flux of an electromagnetic field can inculcate a voltage difference as a mode interference on the line. Compared to common mode noise are tolerant up to 1000 mV with a LVDS transmission the receiver.

The close out lines also result in only a slight emission of the push-pull the desired signal. Still can set unwanted common mode signals that lead to unwanted radiation of an electromagnetic wave at the inappropriate execution of a circuit also along a well-run lead assembly. This, however, can be influenced by a total of EMC-compliant design of the circuit and not only through the cable guide.

In transmission paths in the Gbit / s range are runtime differences between the paths and possibly also to avoid other LVDS channels. In the same conductor lengths are therefore necessary to a synchronous signal transmission. This condition can be achieved by meandering conductor tracks.

LVDS is integrated, for example, for input and output channels in FPGAs. Here give manufacturers such as Xilinx, the line lengths within the housing as so-called "Flight Time" on. Although the name suggests a time value, but it is the cable length in millimeters.

Data rates

The maximum data rate of an LVDS interface will depend on the cable quality. With Cat-5 UTP cable typically has a line length of about 2 m at a data rate of 200 Mbit / s. According to the current state of the art, the limit is several Gbit / s


An important application of LVDS is the digital control of liquid crystal displays ( LCDs). Many computer motherboards that are designed to be installed along with the display in a common housing, have it often in addition to or instead of the usual VGA and DVI ports that can be connected via a jack for an LVDS screen. LVDS signals are used by many liquid crystal displays as an internal signal standard, so you can save expensive converter.

On the motherboard side of the LVDS connector and their availability is not standardized, on the side of the display there are a few common connectors and signal assignments.


The end of 2010 it was announced that AMD from 2013 will not support LVDS for LCD displays more. VGA, however, is still to be two years longer supported. In the future, we will focus on the interfaces HDMI and DisplayPort.