Memory module

A memory module or memory module is a small printed circuit board are soldered to the plurality of memory blocks ( Dynamic RAM in the form of integrated circuits ). Form memory modules or add more memory to electronic devices such as computers or printers and there are inserted into specially designated slots.

The term memory module is rarely used for memory cards or USB sticks.

Designs

Commercial Modular designs for personal computers are, or were:

Single Inline Memory Module (SIMM ) (This is just a series of lines, each of which is represented on both sides by a contact): 8 -bit wide modules (30 contacts) This also occurred in a variant with connector pins, this is called Single Inline Pin Package ( SIPP ) and corresponds to a SIMM with practically soldered to the contact surfaces of pins.

Fast Page Mode (FPM ) DRAM or
Extended Data Output ( EDO ) DRAM

Synchronous Dynamic Random Access Memory (SDRAM, SDR)
Double Data Rate (DDR- SDRAM, DDR )
Double Data Rate 2 (DDR2- SDRAM, DDR2)
Double Data Rate 3 ( DDR3 SDRAM DDR3)
Small Outline Dual In- line Memory Module ( SO- DIMM) for smaller footprint (eg, in notebooks)
Micro dual inline memory modules ( Micro- DIMM)

Manufacturer -dependent modular forms (for example, server ) and those for special requirements are available in large numbers, including DIMM EDO RAM. On the other hand, using other types of devices (printers, RAID controllers) quite popular PC modules.

SIMM memory modules ( asynchronous) are " unbuffered " or "buffered " DIMM memory modules (synchronous, SDR, DDR ) corresponding to " unregistered" or " registered". As a further development of the registered modules DDR2 modules and DDR3 modules have been introduced as a Fully Buffered DIMM (FB - DIMM).

Buffered modules ( buffered, registered, fully- buffered ) when accessing by the latency of the buffer one clock cycle slower, but reduces the electrical load on the memory interface in the chipset or the CPU. This makes such modules especially for server applications with large memory make sense by a higher number of memory modules.

Parameters of a memory

Storage capacity (size)

The storage capacity of a memory module is normally calculated as the product of the capacity of the most similar memory chips and their number.

One example is called a memory module, which is equipped with 16 chips of the type GM72V16821CT10K. From the data sheet, we learn that this chip is organized in two banks 524,288 ( = 219) words with a word length of 16 bits each (2 × 219 × 16). This gives a storage capacity per chip from 2 × 219 × 16 bits = 224 bits = 16,777,216 bits. With 16 of these chips, a storage capacity of the storage modulus of 228 bits = 268,435,456 results bit or - with 8 bits per byte - 225 bytes = 33,554,432 bytes = 32 MiB.

Some memory modules have one or two additional chips ( same or different type), which are responsible for error correction or parity functions. Here often 9 bits are used (8 data bits and 1 parity bit ) for a byte.

Lines

The now common DDR/DDR2-Speicher has 64 data signal lines (or 72 in ECC). Each SDRAM chips are connected such that they occupy the whole width of the data bus. Each chip is responsible for certain data lines. A chip with a "× n " organization can power a number of data lines. Consequently, 64 / n chips with the organization " × n" are required for a data bus with 64 lines. For modules having a plurality of banks ( see below), a plurality of chips ( 2 or 4) are connected in parallel to the data lines. Consequently a module with k benches 64 / n × k contains chips with the organization " × n".

Additional input lines govern the selection of the memory chip (Chip Select) and the read or write direction (R / W) of the data.

Speed

As with the size, it is also distinguished in the speed between the entire DIMM and the individual chips. A single chip always refers to the maximum clock frequency (for example, DDR2 -1066, DDR -400 SDRAM 133).

In all DIMM, however, it comes to data transfer rates (for example, PC2 -4200, PC3200 ). Equipped with SDRAM chips with DDR2 -533, which therefore have a clock frequency of 266 MHz, they transferred the DDR2 mode 4 data words per clock, and you can set the maximum transmission rate, for example, calculated as follows:

64 lines per memory module can transmit 32 bytes per clock 4 × 8 bytes =;
133 300 000 clock cycles / s (MHz ) x 32 bytes = 4.266 billion bytes / s, which is about 4.2 GB / s

The data transfer performance value is only an ideal value and is never achieved in practice. However, it is customary for the classification of memory; So in the example above it would be PC2 -4200 DDR2 -533 from chips that run at 133 MHz ( see DDR2 SDRAM ).

Benches / Ranks

A DIMM can be set up with a different number each of the same modules. The JEDEC committee makes this very specific requirements for the construction of the DIMMs. Allows you to use chips ( with buffer only ), 8 or 16 data lines ( as lines ) either take 4 to complete is. Furthermore, it is always a certain group of DRAM chips each assigned to a bank. A bank or a rank ( according to JEDEC terminology) is a unique, independently addressable 64 bit wider range of memory module ( bit with ECC modules 72). Each bank behaves like a separate memory module. Thus, for example, two-bank modules, the bus lines charge as strong as two one- bank modules. There are memory modules with a couch, two or four banks ( single-, dual - and quad- rank DIMMs ). Since chipsets usually can only manage a maximum of 8 banks (or at high speeds, such as DDR-400 usually only 6 banks ), one has for large memory configuration (eg 8 x 2 = 16 GiB GiB ) on one bank recourse modules because with two bank modules with 4 x 2 banks already all 8 banks were occupied. In addition, the speed of the RAM in such cases must generally be reduced, for example to PC3200 PC2700, otherwise the interference of the lines are too large.

Between the bank number and one or both sides placement of the memory modules with memory chips ( Single-Sided/Double-Sided ) no direct correlation, ie sided loading Modules can include two banks, and double sided modules can contain only one bank.

Buffer

If due to the memory requirements more blocks are required than is permitted under the requirements of the JEDEC Group per data or address line, so-called buffer driver must be used. This decouple the data and address of the module from the external bus, it may be that used, for example, instead of four blocks each of permitted line 8 or 16. The memory module itself then counts only as a single input.

The disadvantage is usually that this buffer itself again have switching times that are added to the access times of the pure RAM modules.

Functioning of addressing

The trigger for a write or read operation in the main memory is mainly the CPU. Also, computer peripherals can access via DMA to the memory, but also there most of the operations of the CPU causes.

Can not find the CPU data within the processor caches or wants to write data directly into the memory, the memory controller will be tasked with. In older Intel CPUs, such as. the Pentium 4 or Core 2 Duo, the instructions on the front side bus to the memory controller, which is located in the Northbridge sent. Newer Intel processors like the Core i-series models as well as AMD CPUs since the introduction of the K8 architecture have a significantly shorter path, since the memory controller is then directly to the CPU.

Timing

There are a number of parameters which control the timing of the memory. By default, a set of manufacturer -time behavior is recorded in the memory module. In modern designs to this is an EEPROM on the bolt, which can be read by the BIOS and thus ensures a correct configuration. Through so-called tuning by the user will often attempt to optimize this timing, but this can lead to system crashes.

DDR memory is labeled in the following way:

In the above example, a RAM with the parameters PC3200U - 30331 -A1 is described. The most important parameter is the maximum speed of the module. " PC3200 " indicates explains in more detail at speeds memory modules that can deliver 3.2 billion bytes per second. Thus you can quite easily determine the allocation of processors / chipsets and matching memory modules. A FSB 400 processor can also send only 3.2 GB / s through its interface. For this reason, therefore, that memory for the corresponding processor would be sufficient. The "U" stands for unbuffered DIMM. After the hyphen, the major latency as expressed in clock cycles follow:

RAS -to -CAS Delay: ( minimum ) length of time between the activation of a row / bank and the dispatch of a read or write commands.
RAS Precharge Time: ( minimum ) length of time between the deactivation of a row / bank and re- activation of a row in the same bank.

With DDR SDRAM, there are chips with a CL of 2, 2.5 or 3 cycles of time, which is why you need two for the CL parameter numbers ( 3033 stands at 3.0 - 3 - 3 ).

DDR2 memory is labeled in the following way:

When DDR2 memory only integer times are allowed why the CL is specified with only a number. In the JEDEC specification, the capacity size is only for DDR2 memory. Furthermore, requires the disclosure to the construction of the bar. " 1Rx8 " stands for a single-rank DIMM that ( x8 ) contains SDRAMs (see Bank), each of which has 8 data pins.

Interesting parameters are the operating voltage together with tolerance range, temperature limits or additional latency as or. Such parameters are precisely defined in the JEDEC specification and are therefore not shown separately. The Activate to precharge time is but like stated, because it is interesting for overclockers. It is usually behind separated by a hyphen, eg PC3200 -2022- 5th

For overclockers also interesting is the Command Rate ( 1T/2T ), although this latency of the memory chips is not an isolated property. This waiting period is then necessary, if many chips are active on the storage channel and in the address lines of the memory controller to be more heavily loaded. Typically, up to 3 ranks ( a double -rank and a single-rank ) to address with 1T, at more must either extend the Command Rate or lower the clock frequency.

Important parameters for the time behavior of the memory are: ==== CAS ( Column Address Strobe) Latency (CL ) - column operations ====

RAS -to- CAS Delay - row operations

Column Address Select or Column Address Strobe, this control signal is applied during a valid column address. The memory device stores this address into a buffer.

Synchronous DRAM (SDRAM, DDR SDRAM) also have the control inputs RAS and CAS, but they have wasted their immediate function. The combination of all control signals ( CKE, RAS, CAS, WE, CS) Instead, with synchronous DRAMs evaluated at rising clock edge in order to decide whether and in what form the signals must be interpreted on the address lines.

The advantage of the savings of the external address lines is offset by an apparent disadvantage in the form of delayed availability of the column address. The column address is required but only after decoding the row address, the activation of a word line and bit line signal of the review. However, this internal process takes about 15 ns, so that the column address delay resulting from reducing.

RAS Active Time () and RAS Precharge Time ()

TRAS: The parameters tRAS (RAS pulse width, Active Command Period, Bank Active Time) describes the time that must elapse after the activation of a line (or a line in a bank ) before a command to disable the line, ( precharge, closing the bank) may be sent. The parameter is given by the fact that the gain of the bit line and the write-back of the information in the cell must be fully completed, before the word line may be deactivated.

TRP: The " tRP " parameter (" Row Precharge Time " ) describes the time that must elapse after a precharge command at least, before a new command to activate a line must be sent in the same bank. This time is defined by the condition that all voltages in the cell array (word line voltage, the supply voltage of the sense amplifier ) are turned off and the voltages of all the lines ( in particular those of the bit lines ) are back to their initial level.

RAS Active Time

The parameters tRAS (RAS pulse width, Active Command Period, Bank Active Time) describes the time that must elapse after the activation of a line (or a line in a bank ) before a command to disable the line, ( precharge, Close the bank) may be sent. The parameter is given by the fact that the gain of the bit line and the write-back of the information in the cell must be fully completed, before the word line may be deactivated.

RAS precharge time

The " tRP " parameter (" Row Precharge Time " ) describes the time that must elapse after a precharge command at least, before a new command to activate a line must be sent in the same bank. This time is defined by the condition that all voltages in the cell array (word line voltage, the supply voltage of the sense amplifier ) are turned off and the voltages of all the lines ( in particular those of the bit lines ) are back to their original level

RAS Cycle Time

This describes the time between two complete cycles from precharge to precharge.

Error detection (ECC )

A memory module can be used depending on the equipment

Without the possibility of error detection
With error detection ( parity)
With Error Correction Code ( ECC)

For the simple error detection using parity bit 8 bit word length is another bit needed, the modules are therefore 9 bits (single SIMM ) organized 36 bits ( PS/2-SIMM ) or 72 bits wide ( standard DIMMs). A single DIMM so that also offers plenty of bit - width for the use of error correction (see below), while this number of similar PS/2-Module must be connected in parallel.

The error correction must also be supported by the motherboard ( chipset and BIOS), the extra bits on the modules provide only the possibility to store the required information.

To detect memory errors, there are several methods. One of these methods comes from the U.S. mathematician Richard W. Hamming: The Error Correction Code (ECC ) is a type of hash value of the 64 bits of each memory line. This redundant information is calculated from the memory controller and stored in 8 additional bits (for 32 bit memory lines there are 7 more bits), which is why ECC memory has 72 bits per line.

ECC can be 1 - and 2- detect bit errors and correct 1 -bit errors. Multi-bit errors may remain unnoticed. ECC memory comes in desktop PCs hardly used.

Other techniques for error detection are known under the name Chipkill, Active Memory, Memory Resiliency or memory RAID.

The main cause of memory errors is non-ionizing radiation (such as earlier believed ), but rather problems of individual memory cells (eg, due to aging or manufacturing issues ).

Comparison Chart

DDR SDRAM

If the memory interface is now dual channel, it can reach twice the data rate. AMD Athlon64 FX processor, for example, has a dual-channel memory interface, the Athlon64 socket 754 in contrast, has a single channel memory interface.

Dual DDR SDRAM

DDR2 SDRAM

RDRAM

Dual RDRAM

The indication of the data rate is only for classification and therefore does not correspond to the user data.

Swell

Computer memory DDR-SDRAM Northbridge (computing) Serial Presence Detect ROM cartridge Semiconductor memory

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