Motorola 68020

The Motorola 68020 is the first true 32- bit microprocessor, the Motorola 68000 family and consists of about 190 000 transistors.

In contrast to the 68000 which, although as a 32 -bit CPU may be programmed internally, but has only a 16- bit ALU, and composed the 32 -bit instructions from a plurality of 16-bit increments, and only a 16 bit data bus has, has the 68020 a 32 bit data bus and a 32- bit ALU, which earned him an enormous speed advantage over the older representatives of the 68000 family.

While the 68000 can be multiplied for multiplying two 16-bit data words into 32- bit data word, the ALU of 68020, two 32-bit data words to be multiplied to a 64 -bit data word. The same is true for the division.

There was also a coprocessor interface with matching FPU ( MC68881, MC68882 later ) and matching MMU ( MC68851 ) in the 68020 instruction set for floating point instructions and MMU commands has been extended. For the former, as previously used by trap commands to be treated the 68000 instruction set, so that one could perform the corresponding code using a single FPU emulation on a 68000 (but taking considerably reduced running speed ). The CPU decoded the imaginary for FPU and MMU command in the microcode and then forwarded them to the appropriate blocks on the coprocessor interface. To keep the number of required lines low, " listening ", the FPU on the data bus and could this also control directly for store operations, the MMU was switched to the memory interface at the address lines between the CPU and the memory controller and modified the data released by the CPU addresses ( thereby slowed down when using the MMU memory accesses, which was only improved by the integrated MMU of the MC68030 ).

In addition to increasing the ALU received the 68020 but also a more complex addressing unit or address generator him especially for its time ( the late 1980s ) brought extremely complex addressing modes. Thus, the effective address is for reading a data word from the RAM are formed as follows: content of a register added with constant is an address at which a data word is read, to which a further constant, and an optional at 0, 1, 2 or 3 be added bits shifted register. The result is the effective address is then read on the actually. Syntax: [( bd, An.x ) od, Rn.x * sc ] These addressing modes are especially challenging in the pursuit of pointers to structures in vectors extremely useful.

This very complex addressing modes with names such as " indirect indexed addressing " represented the culmination of the architecture of CISC processors, at the same time but their turning point: These addressing modes require a lot of micro- code and clock cycles ( it had indeed initially a first address will be formed, which then was used for a memory access to the base address before the read value therein to the bit-shifted value of the index register, if necessary, then could be modified to provide the required access for the address), to be executed. At the same time they were implemented by almost any compiler manufacturers quickly enough to be effective useful. Code that used these addressing modes, was on older 68000 processors can not be executed simultaneously and very hard to debug ( yes they had no more, in the look inside and you could check the address value actually used for the memory access register). Accordingly, almost simultaneously started development on RISC architectures, got along with much less instructions and addressing modes. It was the development of multilayer cache systems with effective management brought in the late 1990s, the CISC processors back against the opponents of RISC families in advantage.

Compared to its predecessor MC68010 nor was added a level-1 instruction cache of 256 bytes.

When the MC68020 address bus is 32 bits wide, so a total of 4 GiB memory could be addressed. The MC68EC020 has a reduced address bus of 24 bits, leaving only 16 MiB memory can be addressed.

Well-known computer systems in which Motorola 68020 processors were used, the Apple Macintosh II, the Sun workstations in the 3 Series, the Amiga 1200 and the Amiga CD ³ ², the latter two with MC68EC020 processor with about 14 MHz, and the control are compensation calculator euro Fighters, without which this could not be kept stable in the air.

The successor to the Motorola MC68020 is the 68030th The biggest change was to accommodate the MMU into the chip, so that the delay was accounted for bus access by the MMU. After the successor Motorola 68040 integrated then the FPU to the main processor.