Motorola 68060

The Motorola 68060 is a 32 -bit processor from Motorola. He was released in 1994 as a successor to the Motorola 68040. The 68060 is the most powerful processor of the 680x0 processor family.

Architecture

The Motorola 68060 (usually just called 060, ie zero - sixty) is not a simple redesign of the 68040, but was brand new - based on the experiences with the 68040 - developed. There was a second unit for integer calculations added ( superscalar ) and an extension for integer multiplication, which requires only two cycles per multiplication. The unit for floating-point unit (FPU ) has been replaced by a faster version, with some more complex functions were of the 68881/68882 not implemented. Even compared to the FPU of 68040 additional functions have been removed, but tremendously adds to the overall execution speed of the 68060 FPU (about a factor of 3.5 ). The lack of functionality must be emulated by a vendor-supplied software library. Furthermore, a logic for leap predictions ( branch prediction) has been inserted. The 68060 has failed in about two to three times the computing power of a 68040 at the same clock. The development team for the 68060 was directed by Joe Circello.

The 68060 has a similar architecture to the Intel Pentium. A portion of the internal logic (some functional blocks ) is not operating in the 68040 compared to the double, but at three times the bus speed. However, this is not comparable to the clock doubling and tripling the DX processors in the PC area. Both processors have two superscalar in-order pipelines. Each pipeline has in each case an instruction decoder. The decoder decomposed complex machine commands into simpler, before they are processed. The internal processing is done in four steps according to the RISC principle. The real difference lies in the Pentium floating point unit is not executed superscalar (FPU ) of the 68060th Either two integer instructions and a branch instruction or an integer, a floating point and a branch instruction to be processed in parallel. However, can not be processed independently of each other all the instructions so that an average IPC yields of about 1.3. Therefore, the 68060 achieved in Gleitkommabereich only about one-third the speed of a Pentium at the same clock. In contrast, the integer multiplication and bit shift (English " bit shifting" ) much faster. The 68060 can also run in the addressing unit simple commands, so that results of the two addressing logic computing cycles before those of the (ALU ) are available. This type of processing results in the zero -cycle branch behavior, that is, a branch usually costs no CPU cycles. For this optimization, a large amount of commercial compiled code is analyzed. In addition, the 68060 features according to the Harvard architecture on two MMUs, one for data and one for instructions paging. The 68060 is mostly binary compatible in the integer range with its predecessors. Some of the more complex addressing modes of the 68020/68030 are not supported. The compatibility in the FPU area is only guaranteed through the use of the emulation library. The MMU has been reduced compared to 68030 and 68040 in the functionality, for example, only page sizes of 4 and 8 Ki Ki are supported.

The 68060 is the first and only member of the 68000 family of energy -saving features. The CPU may different logic blocks dynamically depending on the workload down or up overclock or turn it off completely. The functions can be accessed via software.

The 68060 was the final development of the Motorola 68000 family. Motorola broke the advancement in favor of the PowerPC processors. The 68060 was last used in several later Amiga models and the Turbo card extensions. There were also some Atari ST descendants, who also made ​​use of the last generation. The TOS Compatible Medusa Hades with 68060 processor and expansion cards CT60 and CT63 for the Atari Falcon belonged to it. Apple and most of the Unix world growth after 68040 to RISC -based processors. The 68060 was introduced at a rate of 50 MHz (based on Motorola's 0.6 -micron manufacturing process ). Later models experienced a reduction in feature size to 0.42 -micron and so were at 66 MHz, even partially operated at 75 MHz. Some of the EC and LC variants were even operated at 80 MHz or even 90 MHz. The 0.42 -micron processors were very rare, since concentrated on his Motorola PowerPC processors.

The development of the 68000 core was continued by Motorola for embedded purposes. The core has been extended to additional peripherals therefor. In addition, the complexity was reduced in order to reduce power consumption and manufacturing costs. For these changes, the Motorola ColdFire and the Motorola DragonBall family emerged, which is today in many embedded devices ( such as mobile phones and PDAs ) are used.

History

The processors with even numbers ( 68000, 68020, 68040, 68060 ) were provided for major changes to the architecture. The odd numbers ( 68010, 68030, 68050, 68070 ) were against it for architecture optimizations. The processors 68050 and 68070 were indeed planned, but were never produced.

For example, the Motorola 68010 (and also the peculiar 68012 ) was a 68000 with optimizations for loop operations and the possibility for a page fault ( page fault ) to pause an instruction. This allowed the use of virtual memory ( virtual memory ) under the use of a memory management unit ( MMU). Otherwise, there were no other changes to the architecture. Similarly, it was also at the 68030th This was basically just a smaller version of the 68020, when the MMU and an additional data cache ( 256 bytes ) have been integrated into the CPU. The 68030, there have been at a rate of up to 50 MHz.

In contrast, the changes from the 68000/68010 to 68020/68030 were very extensive.

Variants

• 68060 - complete CPU with FPU and MMU
• 68LC060 - disabled FPU, MMU present
• 68EC060 - FPU and MMU disabled

Technical Features

• Vcore 3.3V
• I / O 5 V

• 8 KiB DCache (4- way set-associative )
• 8 KiB ICache (4- way set-associative )
• 96 byte FIFO Instruction Buffer
• 256 Entry BranchCache
• Entry 64 ATC MMU Buffer (4- way set associative )

• 8x 32-bit data register
• 7x 32-bit address register
• 1x 32-bit stack register (2x available, one for user mode ( USP) and once for Supervisor Mode (SSP ) )
• 1x 32-bit program counter register
• 1x 16-bit status register ( 8 bits for each user and supervisor mode)
• 1x 32bit processor configuration register
• 1x 32-bit vector base register
• 2x 32-bit source / destination function register
• 1x 32bit cache control register
• 2x 32bit root pointer registers ( for each user and supervisor mode)
• 1x 32-bit bus control register
• 5x 32bit MMU registers ( only 68060 and 68LC060 )
• 8x 80bit FPU register ( only 68060 )
• 3x 32-bit FPU status register ( only 68060 )

• ~ 88 MIPS @ 66 MHz
• ~ 110 MIPS @ 75 MHz
• ~ 36 MFlops @ 66 MHz

Trivia

• LC and EC are variants of the CPU, in which on the The errors within the FPU and / or MMU unit were detected during the manufacturing process. In order to increase the yield of the production, the affected units were targeted disabled and the CPU sold cheaper with reduced functionality.
• Viper 1260 ( an Amiga 1200 turbo card ) used a 68060 with 50 MHz overclocked to 56 MHz
• The Apollo 1260 ( an Amiga 1200 turbo card ) can be combined with a 68060 rev.6 to 80 MHz clock
• The CT60 ( an ATARI Falcon expansion card) is reached with processors from the rev.6 clock speeds of 90 MHz to over 100 MHz

Industrial Control Unit: 14500

6800 Family: 6800 | 6809 | (Hitachi 6309 )

68000 family 68000 | 68008 | 68010 | 68012 | 68020 | 68030 | 68040 | 68060 | Coldfire | Dragon Ball

88000er Family: 88110 | 88200

Math coprocessors: 68881, 68882

Memory Management Unit: 68451 | 68851

PowerPC family: PPC 601 | e200 PPC | PPC 603/e300 | PPC 75x | e500 PPC | PPC 74xx/e600 | PPC e700 | PowerQUICC Family | QorIQ

• Motorola processor