﻿ Negated AND gate

# Negated AND gate

A NAND gate (of English: not and - and not ) is a logic gate with two or more inputs A, B, ... and an output Y, between which the logic operation AND NOT exists. A NAND gate is the output from 0 only if all inputs are 1, or is only 1 if at least one input is 0.

## Survey

The notation is the Shefferschern line.

## Use

NAND gate play in digital technology, the role of a standard module, as can be alone with them put together all the logical links and therefore more complex circuits ( such as adders, multiplexers, etc. ). Due to the fact that all other leave with this block replace a circuit is much cheaper. This is because a so-called IC always contains several gates and therefore a given number can provide inputs and outputs. Shall an input signal to be negated only, no new IC must be used, but you put the input pins (connections ) together, so that is only one entrance. So that a NOT gate is formed. With a lower IC number so circuits can be implemented because the hardware modules can be fully exploited.

## Realization

The circuit implementation is carried out, for example, with two (or correspondingly more ) series switches ( transistors), set the output Q to ground ( logic 0) when they are all turned on. If one of them fails, the ground connection is interrupted and the output Q is (logic 1) to plus potential.

NAND standard block in transistor-transistor logic (TTL), a four-way NAND gate 7400 with the label known to a digital IC, used in place of a plurality of transistors having a plurality of emitters, a single transistor at the input. These special transistors are also known as multi-emitter transistor. The previous logic, diode transistor logic (DTL ) was used instead of the multi-emitter transistor diodes for a plurality of input link.

In NMOS logic, a NAND gate having three equivalent N- channel junction field effect transistors ( N-MOSFET ) can be realized with less chip area. The equivalent functionality is also available in CMOS logic with four MOSFETs with lower performance: is present at input A and B high- potential, derived T3 and T4, where T1 and T2 lock. Thus, at the output Y low potential. For all other input states is high- potential at the output, because T1 or T2 is conducting and at the same time T3 and / or T4 locks.

• Technical realizations circuit of NAND gates in different logics:

TTL

NMOS

CMOS

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