NMOS logic

The NMOS logic (of English N -type metal-oxide -semiconductor ) is a semiconductor technology which at Digital integrated circuits, applies and is used for implementation of logic circuits. Exclusively so-called n-channel metal-oxide- semiconductor field effect transistors ( n -channel MOSFET ) are used as specificity.

The NMOS logic was used in the 1970s to the late 1980s for the implementation of digital logic circuits, such as occur for example in microprocessors. It takes place today, except for niche applications, no longer apply. It was almost completely replaced by the CMOS logic ( low power dissipation).

Construction

The structure of the NMOS logic is to be exemplified by a simple NAND gate. Opposite, the equivalent circuit of a NAND gate with both inputs A and B and output Y is represented. The load resistance R, has the disadvantage that it requires on integrated circuits (IC), very large space. In the first embodiment of the NMOS load resistor that has been replaced by a self-blocking n -channel FET, which is required in the circuit exclusively self-blocking n -channel MOSFETs. This had the advantage that less process steps of manufacturing technology in the manufacture of the IC are required. Disadvantages are the necessary two supply voltages.

An improvement is obtained when the upper load transistor is replaced by a self-conducting n -channel MOSFET, as shown in the adjacent figure. This is also the usual switching principle of NMOS logic circuits dar. This can be got by with only one supply voltage and lower losses, disadvantage is the complicated production because of the self-conducting load transistor T1 claimed at least one process step more and more chip area than the switching transistor.

The load acts on the NMOS transistor as an approximately constant current source, so that the cross current is less than a constant value in the load resistor R. If the self- conducting load transistor T1 realizes with low drain / source diffusion, four masks are sufficient for the production of the NAND gate. If the stage is realized with high impedance, at least five masks are required.

In contrast to the easier to be manufactured precursor logic PMOS logic which operates only with the p-channel MOSFETs used in the n-channel MOSFETs in the NMOS have the advantage that act as charge carriers in the field effect transistor only negative charge carriers in the form of electron. Electrons have higher mobility than that of the p -channel MOSFETs involved in the charge transport positively charged electron holes ( " gaps" ) in the semiconductor. The advantage is a higher switching frequency that can be achieved with NMOS gates over comparable PMOS gates.

Due to the progress in the manufacturing method of this advantage, however, of NMOS become negligible, and CMOS, a combination of self-blocking p- channel and n -channel MOSFET is used at much lower currents than in the NMOS cross. NMOS has over CMOS following disadvantages:

• The space requirement is greater, unless it is a high current consumption accepted.
• An NMOS gate has in static mode case with logic 0 at the output of a comparatively large cross current.

An extension of NMOS, at smaller feature size and higher packing density, also referred to as HMOS.