No instruction set computing

The No Instruction Set Computing ( NISC ) ​​is a computer architecture and compiler technology for the development of highly efficient processors and custom hardware accelerators, by a compiler, a control of the hardware at a very low level allowed.

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NISC is a statically - scheduled horizontal nano -encoding architecture ( SSHNA ). The term " planned static" means that the process execution, as well as error control are in the hands of the compiler.

The term "horizontal nano - encoded " means that NISC does not use a predefined set of commands or microcode. The compiler generates code for direct control of the nano- instruction set, or microcode.

The compiler generates nano codes for direct adaptation of the arithmetic units, the register of the multiplexer as well as the bus system.

It gives the compiler the control on a deep level for better utilization of the bus system resources, which ultimately leads to better performance.

The advantages of the NISC technology are here:

  • Simple controller: No hardware scheduler, No instruction decoder
  • Better performance: More flexible architectures, better resource utilization
  • Simplified design: no need for designing instruction sets

In essence, NISC is based on the concept, bringing powerful FPGAs with intelligent compiler to programs that were written for example in high-level languages ​​such as C, to understand in real time in FPGA hardware description languages ​​like VHDL or Verilog translate.

EDA developers have devised for methods by which FPGA systems can be implemented without VHDL and implement already a standard ANSI C source code directly into a digital circuit equivalent. Both of FPGA vendors Altera ( C2H compiler) as well as EDA specialist Altium (CHC compiler) have been developed such compiler. This also programmers access to the FPGAs enables previously had no knowledge and experience with VHDL and Verilog.

Assuming that a standard is developed regularly brings all the program fragments in FPGA - oriented form, the FPGAs in the way local PCs could thus be opened, instead of the usual still hardwired processors.

1-bit architecture Bit slicing 8-bit 32-bit architecture Explicitly Parallel Instruction Computing Microarchitecture Floating-point unit
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