OR gate

An OR gate is a gate with multiple inputs and an output, wherein the output if and only returns 1 if at least one input 1 is present. It corresponds to the logical OR. In Boolean algebra, the OR operator is or (origin the Latin word " vel " (or) is ) is shown and is also called a disjunction.

Survey

The greater- equal sign ≥ shows the currently valid in Germany circuit symbol that at one or more ones at the inputs (high, logic 1), the output is 1.

OR gate with a larger number of inputs

The minimum OR gate has two inputs ( OR2 ), but there are also gates with more inputs. Should be limited to gates with a certain number of inputs can be realized with these gates also with a higher or lower number of inputs. To increase linked to more gates, as shown in Figure 1 and 2 to see. One should keep an appropriate structure as possible to reduce the gate delay and the required number of gates.

If you, however, required gate with a smaller number of inputs, must be the inputs are not required to logical 0 ( often mass, zero potential ) place, see Figure 3, Figure 4 shows the circuit symbol for an OR gate with three inputs is shown. OR gate with more inputs are drawn accordingly.

Figure 2: OR 4 gate from OR2 gates to unfavorable way

Figure 3: OR3 gate reduced to a OR2 gate

Figure 4: OR3 gate

Technical circuit realization

OR gate are produced as an integrated circuit (IC) by many manufacturers. Standard modules of this type are, for example, available under the designation " 7432 " in TTL technology and " 4071 " in CMOS technology and includes four OR gates each having two inputs. The exact component name depends on the manufacturer. Logic gates of this type are available for a few cents at most electronics stores.

Figure 6: Implementation of an OR gate with relay

CMOS

The figure shows the circuit diagram of an OR gate in CMOS technology. The transistors T1 to T4 together form a NOR gate. If, for example, to input A or B of high potential, then passes T3 and T4, where T1 and T2 is off. At the output of the NOR gate transistors T5 and T6 realize the functionality of a NOT gate. A negated NOR gate give the desired OR gate. With said input assignment of A and B is at T5 and T6, a low potential and T5 conducts, but T6 is off. This results in the output Y high potential.