Physical design (electronics)

In layout design of an electronic circuit ( circuit, multi-chip module, PCB ) is understood as the creation and verification of the geometrical arrangement of the cells or elements and their compounds. The verification within the layout design includes i.Allg. testing of the designed layouts complying with all technological and electrical rules.

Layout (layout synthesis)

When creating the circuit layout is converted with the use of library and information technology, the netlist of a circuit in their real geometric representation. Here, their spatial arrangement, all the circuit elements ( cells / gates, macro cells, transistors, etc. ) are represented in their geometric image ( shape, dimensions, layer assignment) and ( placement) as well as the specific compound structures ( wiring ) is determined between them. As a result, the layout of the circuitry is available, which is used by a layout verification for the production of the module ( circuit multi-chip module, printed circuit board).

Because of their complexity, the layout is divided into individual sections. In digital circuit or chip design, it is common for the steps partitioning, floorplanning, placement, global and detailed wiring and possibly compaction perform. Major steps in printed circuit boards are the placement of the components and the PCB layout.

The automated layout design of integrated circuits is often referred to as a layout synthesis.

Layout verification

The layout follows a comprehensive verification of the layout to its technological feasibility, the electrical correctness and its electrical performance.

When DRC ( Design Rule Check) to verify the feasibility of the layout, by ensuring that the technologically -related design rules is controlled in the layout representation.

Also for the verification of the circuit layout is the extraction, are processed at the layout information for verification. Thus, for example, from the layout netlist extract, which is then reacted with the derived from the circuit diagram ( original ) netlist checked during LVS (layout versus schematic ) for equality to determine the electrical correctness of the layout. In the parameter - extraction or parasites whose electrical parameters are derived, in order to then use, including the netlist to validate the electrical characteristics of the circuit layout from the geometric properties of the layout structures.

When ERC ( Electrical Rule Check) to examine the electrical performance of the layout, such as compliance with a maximum resistance value between two network connections.

From the layout to the integrated circuit

The layout information, often to the the circuit completed institution, the so-called Fab or Foundry passed in the form of GDSII or OASIS data. This process is still referred to as "tape out", although the data transmission is no longer as previously takes place by means of magnetic tape. To this end, the location -specific layout information is first implemented in photolithographic masks in a mask work. These masks are used in the fab for exposing the photoresist on the silicon contained in technologically well-defined mapping steps of the layout. By means of photolithographic masks can thus define areas on the silicon, where materials applied are to be changed or removed. Thereby, a plurality of parallel integrated circuits on a silicon wafer, the wafer. The individual still unpackaged circuits, called This or bare chips are tested on the wafer ( pre-) and as "good" or in "bad". Finally, the wafer is diced into individual dies. The "good" marked this be connected and packaged in a circuit housing.

From the layout to the PCB

Result of the layout design are the so-called Gerber files for PCB manufacture. These describe for each layer ( Layer Sheet ) are the coordinates of the polygons that define the circuit lines, and the diaphragms ( Sheet Apertures) of the photoplotter. In addition, is required for the production or files, which describe the position and the diameter of the holes and the coordinates of the Leiterplattenkontour or cutouts. These are tool- dependent.

Before finishing usually several PCBs are combined into a so-called lot to take advantage of standing in the production of available board space as possible.