PicoBlaze

As PicoBlaze a usable only in FPGAs and CPLDs from Xilinx processor family is called. The processors do not exist as physical hardware, but are available as so-called soft cores, which makes its expansion by adding peripherals to small microcontrollers very easy in the hardware description language VHDL and Verilog.

Thanks to the special optimization of the particularities of certain FPGA / CPLD devices from Xilinx logic requirements of the processors is very low. The disadvantage is that PicoBlaze processors can only be used on FPGAs and CPLDs from Xilinx by optimizing and by legal restrictions and must.

The strength of the PicoBlaze processor is in use as a Finite State Machine, but these should not be particularly time-critical. Implementation of Finite State Machines directly in the hardware description language are strongly dependent on size depending on the size of the states, which can be avoided by the use of a PicoBlaze processor. As a result, the development of the rest of the hardware simplifies. Due to a comparably low power scope of PicoBlaze processors other, more powerful processors and microcontroller should be used as the also available from Xilinx FPGAs as softcore MicroBlaze with complex tasks.

PicoBlaze processors were called KCPSM originally, which is an abbreviation for Constant ( k) Coded Programmable State Machine. Is often mistakenly assumed KCPSM is an abbreviation for Ken Chapman's Programmable State Machine. Ken Chapman is the developer of the PicoBlaze processors in Xilinx.

PicoBlaze family

The PicoBlaze processor family includes the following derivatives:

  • PicoBlaze CPLD (optimized for Xilinx CoolRunner II CPLDs )
  • PicoBlaze (optimized for Xilinx Virtex- E and Spartan-II/IIE FPGAs)
  • PicoBlaze II (optimized for Xilinx Virtex- II FPGAs)
  • PicoBlaze 3 (optimized for Xilinx Spartan-3 and newer Spartan, Virtex -II, Virtex- II Pro, Virtex 4 and Virtex FPGAs newer )
  • PicoBlaze 6 (optimized for Xilinx Spartan- 6 and Spartan newer, Virtex -6 and Virtex FPGAs newer )

Hardware features

PicoBlaze processors based on an 8 -bit RISC architecture. The rate varies greatly with the hardware used, but can reach well over 100 MIPS. For the execution of an instruction every two clock cycles are required.

Instruction set

The PicoBlaze has a small instruction set, which is limited to the most important commands.

For further details about the commands, the application notes can be consulted (see links).

Programming

The PicoBlaze processors are programmed only in assembly language because of its practical simplicity. Since there is only the part of Xilinx DOS compiler, various integrated development environments have been brought forth by the community, which provide both editors and compilers and simulators available.

PicoBlaze processors are usually not as conventional processors or microcontrollers programmed directly, because the access to the program memory from outside the FPGAs / CPLDs is limited. Instead, a pre-initialized VHDL / Verilog program memory instance is created using one of several compilers, which can be integrated with the processor instance together in their own circuit. The compilers use this a VHDL / Verilog template, which will be read and completed. Thus it is possible, to the program memory type to influence, which allows the use of dual-port memory blocks of program memory.

When using dual-port memory blocks as program memory can optionally two PicoBlaze processors with the same storage / work program or the program memory can be changed using additional logic at runtime.

Troubleshooting

Because access to the internal processor hardware in the FPGA / CPLD is not possible PicoBlaze processors may not be as conventional processors or microcontrollers diagnosed directly at runtime. PicoBlaze processors are seamlessly integrated into the rule in your own VHDL / Verilog code, which is why that fact is not lost because, in general, all the code ( VHDL / Verilog, PicoBlaze program) should be diagnosed with a VHDL / Verilog simulator, as a malfunction of the FPGA / CPLD may be caused both by the VHDL/Verilog- and by the processor code.

For the abstract contemplation of the processor codes different PicoBlaze simulators are available.

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