Programmable logic device

A programmable logic circuit, often referred to in the German-language specialist literature as programmable logic device PLD, or shortly, is an electronic device for integrated circuits. Unlike logic gates, which have set a fixed function, PLDs obtained only after the production of their function by the corresponding programming ( configuration).

Distinction on the complexity

Examples of different complex PLDs are ( in ascending complexity):

Simple programmable logic circuits are usually followed by an array of OR operations of an array of AND operations.

  • Programmable Read - Only Memory (PROM ) PROM is a fixed AND array with a programmable OR array or a lookup table (LUT) dar.
  • Programmable Array Logic ( PAL) or Generic Array Logic (GAL ) PAL is a programmable AND array with a fixed OR array represents a GAL is in contrast to a PAL rewritable.
  • A programmable logic array (PLA ) In a PLA, both the AND array and the OR array is programmable.

PLAs were usually used to replace the so-called glue logic. Meanwhile, they are rarely used and have been replaced by the following PLDs.

  • Complex Programmable Logic Device ( CPLD ) A CPLD consists of blocks that contain a PLA, the input and output blocks and a programmable feedback. These blocks may be interconnected. Usually included for each I / O pin and a flip -flop.
  • Field Programmable Gate Array ( FPGA) An FPGA is similar to a CPLD of interlinked blocks, but these are more complex. A block here comprises flip-flops and LUTs. The possibilities for these blocks to connect with each other are compared to the CPLD greatly expanded. An FPGA includes many finished functional blocks such as RAM, or PLLs all CPU cores.

CPLDs such as FPGAs also often have programmable I / O cells, which allow various signal interfaces (eg, TTL, PCI, or LVDS) to the block to join. See also: Differences of CPLDs FPGAs

Distinction by programmability

  • Mask programmed Here the configuration is already determined in the production of the component. If FPGAs are used in large quantities, they can be ordered mask programmed by some manufacturers. This saves additional production steps and the necessary configuration for external components.
  • One Time Programmable ( OTP) Here are the programming by blowing of compounds ( Fusible link) or the creation of compounds in the antifuse technology.
  • Erasable Programmable Read Only Memory (EPROM ) The EPROM programming is usually only used in PLAs.
  • Electrically Erasable Programmable Read Only Memory ( EEPROM), or flash GALs are programmed EEPROM and can therefore be reused as opposed to PALs. The configuration of CPLDs is usually held on the flash memory. Programming via EEPROM or Flash has the advantage that the component becomes available immediately after power- fully configured.
  • SRAM based The configuration of FPGAs is typically based SRAM. This needs to be charged after power FPGAs only in the block, either through a configuration PROM or a connected microprocessor. An FPGA can even be reprogrammed during operation in whole or in part, such as to change a running processing algorithm. One application of this is the Reconfigurable Computing.
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