Sandy Bridge

The Intel Sandy Bridge microarchitecture is developed by Intel microarchitecture, on the basis of the first models were introduced in January 2011. " Sandy Bridge" based in part on the previous architectures " Core" and " Westmere ", with some elements even come from the NetBurst architecture. Intel itself refers to Sandy Bridge processors as " 2nd Generation Intel Core Processors " and Ivy Bridge processors as " 3rd Generation Intel Core Processors ".


Originally, the Sandy Bridge architecture has been developed under the code name " Gesher " was first presented at the Intel Developer Forum 2006. At the IDF 2007, the name was then changed to " Sandy Bridge".

The Sandy Bridge architecture has been developed by the same development team that the core architecture already brought out (Intel 's Israel Development Center, IDC, in Haifa). Compared to the Nehalem architecture that comes from another development team, the pipeline was again shortened while it was extended at the Nehalem architecture from 14 to 16 pipeline stages.


Due to the further integration of components such as the graphics processor (GPU) and the design of the architecture for more than four cores, Intel has built the architecture modular and said goodbye to the classic crossbar to connect the last level cache (L3 cache). Instead, the cache with cores, the memory controller and the GPU with an internal ring bus are connected. This ring bus consists of four links: a 256 -bit data ring, a "Request -Ring" ( request = request ), an "acknowledge -Ring" (acknowledge = confirm ) and a snoop ring ( snoop = eavesdrop, spy ). The ring bus proceeds via the cache and assumes no additional die area to complete. When clocked at 3 GHz processor Intel estimates the bandwidth per connection to theoretical 96 GB / s

One of the most comprehensive architectural changes is the successor of the SSE4 instruction set. The new instruction set extension is now referred to as AVX, which for Advanced Vector Extensions stands (German: advanced vector extensions). While SSE4 expects to 128 -bit wide registers, 256-bit wide registers are needed for AVX. By twice as wide register up to four floating point or integer operands can now be summarized in a vector, and then normal arithmetic or logic operations are performed by the vector. Due to the introduction of 256 - bit instructions, Intel has known from the NetBurst architecture "Physical Register File" (PRF ) reintroduced. While the core and Nehalem architecture, the operands were always carried and therefore needed additional buffer that would have with the big 256- bit instructions must be further increased, can be dispensed with the PRF to these additional buffer because now with a pointer ( pointer variable ) on PFR these operands are achievable. The processing of 256 - bit instructions is done by interconnecting with the floating point SIMD integer pipeline, which is achieved by means of additional transistors, in addition, some features have been exchanged between the pipelines. This approach eliminates the drilling of a pipeline of 128 -bit registers 256 -bit register, but also the possible throughput is smaller. In addition, the current implementation supports no fused multiply - add (FMA ) with 256- bit instructions.

Another new feature of the so-called " dynamic turbo mode" has become known. In addition to the functions which are known from the Nehalem / Westmere architecture, Sandy Bridge processor cores can increase their turbo -stroke short of the TDP addition, if the processor was previously in idle and thus can be loaded higher in the short term. For continuous loads, the processor controls then back down to the prescribed TDP. While the graphics unit for mobile offshoot " Arrandale " the Westmere architecture has been overclocked yet by drivers in special cases, binds the Intel GPU in Sandy Bridge now with the hardware-based turbo mode on. As with the Nehalem / Westmere architecture, a "Power Control Unit" is installed, so a microcontroller that monitors the energy flows and controls. The cores with caches, the graphics unit and the integrated north bridge ( memory controller and PCIe, DMI ) are each connected separately to its own power supply and can be dynamically adjusted to match the load.

Ivy Bridge

Ivy Bridge was presented on 23 April 2012. Processors based on Ivy Bridge will be manufactured in a 22 nm manufacturing process, which no longer corresponds to the hitherto conventional planar technology, but uses so-called multi- gate field-effect transistors. However, it remains largely the same Sandy Bridge architecture, at least as far as the processor cores, because there only minor optimizations are performed. The integrated graphics, however, the first to support DirectX 11, OpenGL 3.1 ( OpenGL 4.0 since the beta drivers) and OpenCL. In addition, it is significantly more powerful and gets her own L3 cache.

The successor to Ivy Bridge appeared in 2013 and is codenamed Haswell.