Scan chain

Scan test referred to in ( advanced ) digital circuits, a specific method for testing for structural (i.e. manufacturing-related ) damage. It is based on a series connection of all the flip-flops used in the design with an activation mode, so that (Shift mode) or the normal mode, the circuit can be switched back and forth between a serial mode to the series connection. The first and last flip-flop are connected to a particular input or output in the circuit, so that certain test patterns can be read out and pushed into the circuit. With the appropriate switching strategy between Shift and normal operation and a given input bit results in a particular output bit, a structural error must be assumed for the non-occurrence of which leads to the sorting out of the circuit. All members of this test method, the generation of the series connection (scan chain) and the generation of the input pattern for supplying and output pattern of the comparison are incorporated by software tools: the scan- insertion, usually within the framework of the synthesis and ATPG: Automatic test pattern generation.