Semiconductor device fabrication

The term technology nodes (english technology node) referred to in semiconductor technology is a milestone for the definition of a manufacturing process generation and refers mainly to the smallest photolithographically structure size. Since 1997, he is defined by the International Technology Roadmap for Semiconductors ( ITRS ). The term itself is very abstract and only broadly describes the technological advancement in the industry. Thus, the techniques used differ not only between the different manufacturers in a technology nodes, but also between the products of one manufacturer (especially for contract manufacturers, so-called foundries ) with the same technology node. Furthermore, there is no fixed relation to the gate length.

Description

The technology node generation is described in terms of a numerical value, the " half pitch " refers to the so-called (Eng. half pitch ) of DRAM devices refers, for example, half the distance between the two conductors and vias of a periodic structure in the first wiring level. Typical figures are " 65 - nm technology node " or simply " 65 - nm technology " (sometimes called " 65 - nm technology " or " 65 - nm manufacturing "). Was before 1999 instead of the usual statement today in nanometers an indication used in micrometers, for example, 0.25 -micron technology, or 0.8 -micron technology.

Since the value of the specified technology node specifies only half the distance width of dense lines or grave structures, the minimum gate length of a field-effect transistor can be smaller and is not accurately determined on the technology node. For example, can be 50 nm or less at a 65 -nm process, the gate length. The value of the technology node identifies is not directly the smallest manufacturable with photolithography structure.

It is further noted that in the specification of a given technology node, only a rough position of the manufacturing techniques used, may be closed. Based on a producer components of a technology node have been largely manufactured with the same techniques. Such a comparison between the products of different manufacturers is no longer possible not later than the end of the 1990s, there are different manufacturing techniques partly strong. Examples include the use of copper instead of aluminum in the wiring levels or the use of so-called high-k metal gate technology.

The classification of individual microelectronic components is also not mandatory, so that for example, deviate some manufacturers of memory chips or graphics chips more of this grid or not to use such a classification and use intermediate structure sizes.

History

In the initial phase of microelectronics in the 1980s, new technology nodes have been introduced without taking into account defined scaling relations. With shrinking structures it was necessary to find better definitions of technology node with a specific target size for the scaling factor. Here, a factor 1 / √ 2 = 0.7 was fixed between successive nodes, so a 30 percent reduction of the lateral dimensions, which means an approximate halving of the area. However, this factor was especially in recent years not consistently angewendet.Aus this reason, there were also changes in the timetable for the next technology node, for example, with the 2001 ITRS Furthermore, have just been in the DRAM area also intermediates such as 80. - nm or 40 -nm node introduced.

180 - nm technology node

The 180 - nm technology node was introduced in 1999 by leading semiconductor manufacturers such as Intel, Texas Instruments, IBM, and TSMC. In this case, some manufacturers introduced the first time ArF excimer laser with a wavelength of 193 nm ( KrF excimer laser rather than 248 nm ) for the manufacturing of the critical layers ( gate contacts, etc.), such as an Intel Pentium III ( Copper Mine). Some manufacturers (mainly foundries ) use this technology to date (2011), for example, Microchip Technology and Parallax Propeller, because the structure sizes are available for the desired products, for example in the automotive sector, is sufficient. Furthermore, the processes are mature and can therefore with a high yield ( engl. yield ) are driven.

130 - nm technology node

Based on the research results of the IBM Alliance, AMD introduced the 130 - nm technology node first (2002) low-k dielectrics (k stands for the relative permittivity of a material) as insulation between the upper interconnect layers (about level 8 to 11) one. Furthermore, the first (2003), so-called silicon-on -insulator wafer ( SOI wafer ) rather than bulk silicon wafers were used. The advantages of this more expensive substrates are mainly a higher switching speed of the transistors and the reduction of leakage currents between different (electric) active regions.

90 - nm technology node

The 90 - nm technology node was first introduced in 2002 in the industrial production ( first commercial products). For the production of critical levels, the photolithographic processes were enforced with ArF excimer laser, since no other processes were with the necessary resolution available. Furthermore, AMD conducted its first elongated silicon to improve the carrier mobility in its products.

45 - nm technology node

The 45- nm technology node was first used by Intel and Matsushita in production in the year 2007-2008. Other manufacturers such as AMD, IBM, and Samsung followed a little later.

The most important change in the production was the introduction of high -k materials and the use of a metallic gate electrode by Intel (see high-k metal gate technology). Thereby, the leakage current may be significantly reduced by the tunneling transistor.

32- nm technology node

While either immersion lithography or double patterning method was used in previous technology nodes, now all manufacturers must use both technologies to manufacture these structures in a reliable way. Manufacturers such as TSMC, which skip the process, using both technologies at 28nm half -node process. High-k metal gate technology is widely used in the manufacture of central and graphics processors and APUs.

The first processors that were mass-produced in 32nm technology, Intel's Core i3 were and Core i5 processors, which were published in January 2010. It was not until over a year later was followed by rival AMD with the sale of its first commercially available 32- nm processors. These are models of " Llano " - based products from AMD's Fusion series. Other than Intel came here again SOI substrates used.

22 - nm technology node

With the introduction of the 22nm technology node want some manufacturers, primarily Intel, make a change in the type of transistor used in the large-volume production of integrated circuits. They walk away from the decades-long used planar process, to so-called multi- gate field-effect transistors ( engl. multiple gate field - effect transistor, MuGFET ) such as tri- gate FETs and FinFETs. The first processors in this technology are the Intel Core i processors of the 3rd generation. Processor analyzes a cross section showed that Intel apparently uses a gate pitch of 90 nm, which corresponds to a half-pitch of 45 nm. Thus, the assignment of this technology node Intel processors differs significantly from the previous position on the half-pitch.

However, this conversion of the transistor type do not all semiconductor manufacturers, so have Globalfoundries and TSMC - two of the three largest contract manufacturer of semiconductor products, known as foundries, and also technology driver - announced that it will offer its customers in the 22 -nm and 20 - nm technology node processes will be offering in planar technology. The increasing leakage currents are here, for example through new SOI substrates are manageable, in which a very thin semiconductor layer can be driven completely into depletion -on-insulator (English full depletion silicon-on- insulator, FDSOI )

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