Shift register

A shift register is a logic switching device. Many series flipflops push their memory contents ( 1 bit each ), with each stroke to a flip-flop on - clearly seen like a bucket brigade. The number of live registers memory locations is constant.

Shift register function according to the FIFO principle. The first memory stored bit leaves the memory first. The in and out pushing, the A - and the reading done synchronously, a shift register can only be partially used as a queue.

Often one extended shift registers with additional logic (consisting of several logic gates ). This can ensure

• That the highest bit is shifted into the least significant bit (ie it takes place a rotation, one also speaks of a circular shift register )
• That it can be operated bidirectionally, that is the direction of displacement is variable,
• Can be determined whether the released bit is to be set or cleared, and / or
• That you can write or read the register in parallel.

• 2.1 serialization and parallelization of bit patterns
• 2.2 bit shift in machine languages
• 2.3 Multiplication of binary numbers
• 2.4 Use as a buffer
• 2.5 Generation of pseudo-random numbers
• 2.6 Cyclic Redundancy Check

Construction

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The 4 -bit shift register shown in this figure is mainly based on the actual shift register composed of flip-flops D00, D10, D20 and D30. The terminals are defined as follows:

• About the connections d0 to d3, a value can be read in parallel.
• About the terminals Q0 to Q3 of the stored in the shift register value can be read out in parallel.
• About the Data In port ( DI), a value can be read serially and the Data Out ( DO) are read out serially.
• To control the ports clock ( CLK), Load ( LD) and Enable ( EN ) can be used.

The operation will be explained in more detail.

Data - In and Data-Out

The data-in and data-out ports can have different functions depending on the configuration:

• Serial reading on data-in - port and serial output of data on Data-Out port.
• Establishment of a register ring by connecting the data out to the Data In connector.
• To process serial expansion of the shift register by a further shift registers to larger word widths. For this, the Data-Out port is connected to the Data In connector of the next shift register.

Clock

( D10 → D21, D00 → D11 etc. ) With a positive edge at the clock input, the stored in the flip -flop bit is output at the output, characterized by the following entry gate passed and held until a re- positive edge at the clock input occurs.

Load

Is the Load input is set to high, the input to the gates ( D01, D11, D21 and D31 ) applied bits of the upstream flip- flops (or DI input ) are read. Is the Load input contrast to low, the bit of the upstream flip -flop is ignored (or DI input ) and instead read the bit at the corresponding parallel input. The read bit is in this case passed to the subsequent flip-flop (or DO- output).

Does not require a parallel read, the gates D01, D11, D21 and D31 may be, as well as the inputs D0 to D3 are omitted and the outputs of the flip-flop (or data in ) is directly connected to the inputs of the succeeding flip -flop (or Data-Out ) are connected.

Enable

The Enable input controls the output buffer, consisting of the gates D02, D12, D22 and D32, at. With a positive edge the stored in the shift register bit pattern is taken from the output buffer and output at the output parallel with the terminals Q0 to Q3. The value is maintained until a new positive edge at the enable input.

If no output buffer is required, then the enable input and the gates D02, D12, D22 and D32 can be omitted. The outputs Q0 to Q3 are connected in this case directly on the output of the associated shift register flip -flops.

Construction of a bidirectional shift register

In order to achieve a bidirectional shift register, either two shift registers needed, or tri- gate that can switch the internal connections of the register dynamically.

In the realization with the help of two shift registers, the parallel input of a register is connected in a crossed fashion to the parallel input of the second register and vice versa. This value can be copied from the shifting to the left tab in the pushing to the right register and vice versa.

Use

Serialization and parallelization of bit patterns

Shift registers are part of converters between serial and parallel data. Using shift registers then, to realize a serialization or parallelization of bit patterns. During serialization, it has to be possible to load the respective bit pattern in parallel into the shift register, i.e., each flip-flop requires a load input. Otherwise, yes would be before a serial representation. In a parallel flip-flop corresponding to each must have a readable output, so that at a particular time the values ​​of the entire shift register can be read in parallel.

Bit shifting in machine languages

Most computer languages ​​have a shift command on the registers. This allows you to machine language by shifting and adding multiply many times faster than using the generic multiplication instruction / multiplication algorithm. Thus, for example, multiply rapidly at 320, by first copying the register, then a register of 8 bits pushes ( multiplied by 256) and the other register of 6 bits pushes ( multiplication by 64 ), and then adds the two registers. Furthermore, when pushing the fallen out bit it will not fall off, but usually in a flag of the flag register and can then be further processed. A distinction is logical and arithmetic pushing when pushing. When arithmetic pushing this positive numbers positive and negative numbers remain negative. To the most significant bit is not changed.

Multiplication of binary numbers

The multiplication of two binary numbers is performed by shifting and adding (for Example by the Booth's algorithm). This is accomplished in microprocessors by shift registers. A data signal so it is pushed further. For example, a signal "high" state is present, it is shifted to the next bit.

Use as a buffer

For filtering of digitized signals, a signal processor buffers a fixed number of values. This can be done in shift registers.

Generating pseudo- random numbers,

For the generation of pseudo-random numbers with linear feedback shift registers may be used.

Cyclic Redundancy Check

The cyclic redundancy check (English: Cyclic Redundancy Check, CRC) can be performed with a feedback shift register with XOR gates in hardware.

Blocks

The following table lists some standard shift registers are listed by way of example: