Socket 5

The base 5 is a processor socket and the successor to Socket 4 It is intended for early Pentium processors of type P54C. Later versions of the P54C and P55C, however, the successor to the use, in its original form to the base 5 largely compatible Socket 7, which could accommodate all provided for the base 5 CPUs.

The bus protocol of the base 5 is similar in many parts of the base 4 -added connections relate exclusively to the simplified dual -processing, the now integrated into the CPU Advanced Programmable Interrupt Controller - APIC called - and the power saving modes of the new Pentium - type. Ceased however, are a few less important or in practice rarely used terminals of the first Pentium - type P5. In addition, Intel has, for reasons of power consumption, the power supply on the base 5 to about 3.3 volts - depending on the CPU used - reduced. Correspondingly, the logical signal levels have changed, but the signal timing still largely corresponds to that of the base 4

A new pin, the BF -pin, allows the base 5 beyond the setting of various clock ratios between the processor bus and processor core. Many Socket 5 motherboards allow the setting of this pin with a jumper, BF or BF0 - called jumpers. The first Pentium P54C only work with bus clock: core clock ratio of 2:3, later ( Pentium-120/-133 ) then with a ratio of 1:2. With the BF0 jumper then you could already choose the Pentium-120/-133 between these two conditions.

The base 5 was soon replaced by the, in its original form virtually the same function Socket 7, which takes a BF jumper those two, even three had later. Core clock ratios possible: the set of up to four or even eight different bus clock - That was - depending on the used CPU.

It is incomprehensible that Intel first ever distinction between base 5 and base 7. Functional was initially between the two a much smaller difference than that between the early and late, provided for the Pentium MMX Socket 7 type.

The base 5 is - as the Socket 7 - a ZIF socket for Staggered pin grid array layout ( SPGA ), ie the rows of contacts are staggered, in order to achieve a higher packing density.

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  • Processor Socket