SSE5

SSE5 Streaming SIMD Extensions ( 5) was a planned set of instructions from AMD for x86 processors. It consisted of 47 commands that should be especially suitable for accelerating certain algorithms, such as FFT, DCT, or encryption with AES. Among other SSE5 contained so -called three -operand instructions that store the calculation result is not in one of the two source register, but in a third, potentially leading to fewer instructions in the program code and thus to a higher execution speed. The instructions themselves were based on 128 -bit operands and could therefore operate, inter alia, up to four 32 -bit values ​​at the same time. AMD was planning to install a SSE5 butterfly in Bulldozer core.

Even before the introduction of the AMD Bulldozer architecture, however, predisposed to. First, AMD announced to postpone bulldozer at least 2011, which meant at least another year delay from the original schedule in 2009 and the former shift to 2010. On 6 May 2009, AMD announced in his Techblog that SSE5 was painted in the original version. Instead, you have Intel's upcoming AVX SIMD model adopted, provided that takes 128-bit wide registers as SSE5 and since SSE usus now can provide 256-bit wide registers. Apparently did not experience a second 3DNow! Disaster you. At that time (1998) AMD had ever tried to establish its own, incompatible with Intel SIMD extension - and failed to SSE and following.

In the original version of the specifications contained Intel AVX called FMA4 commands, so instructions that could process four operands. AMD adopted this specification 1:1. In the latest Intel AVX specification of January 2009 is of FMA4 but nothing more to read. AMD will support the new FMA3 commands also originally planned FMA4 commands is therefore not emphasize this and continue to provide.