Streaming SIMD Extensions

The Streaming SIMD Extensions ( SSE), formerly Internet SIMD Streaming Extensions ( ISSE ) is a technology developed by Intel instruction set extension to the x86 architecture, which was introduced with the introduction of the Pentium III ( Katmai ) processor 1999 and therefore initially the name Katmai New Instructions ( KNI ) wore. Purpose is to speed up by parallelizing programs at the instruction level, called SIMD.


In contrast to the previously published MMX instruction set SSE has been specially developed for floating-point data types, also own and twice as wide 128-bit registers have been implemented, both often criticized weaknesses of the MMX instruction set. Intel also decided to completely neuzuentwickeln the SSE instruction set and not to make them compatible with the 3DNow instructions already published in 1998 by rival AMD, which fulfilled a similar purpose. This step was successful in the long term, SSE prevailed over 3DNow and AMD later supported also only SSE and was phased out support 3DNow.

Although initially explicitly mentioned in the name ( ISSE ), this technique has nothing to do directly with the Internet; Rather, the reference of the better marketing served (Intel promoted the introduction of the Pentium III, inter alia, the fact that the Internet would be surfing faster and generally more exciting ). After a short time, Intel dropped the "I" omitted, so that we speak today only of SSE.

SSE development

The existing for quite some time competition between AMD and Intel on the definition of sovereignty in the development of the x86 architecture led for about SSE3 to incompatible extensions of SSE.

SSE2, SSE3, SSSE3, SSE4, SSE4a and SSE5 are younger extensions or expansion proposals from SSE from both AMD and Intel. Meanwhile exist with Advanced Vector Extensions, XOP and CVT16 further development branches.

Technical structure

The SSE instruction set extension which originally included 70 instructions and 8 new registers ( XMM0 to XMM7 ), and later the development of both number of registers and instruction number in the course were increased.

As AMD's 3DNow extensions SSE is also primarily designed for floating point operations. However, Intel introduced the Pentium III new 128-bit wide registers a, so that with SSE instructions twice as much data can be processed in parallel at once as with the based on 64- bit registers 3DNow. However, this was not associated with the then processors with a higher calculation throughput as the 128 -bit SSE instructions are divided internally into two 64 -bit SSE Micro- Ops, because the internal execution units and their data paths only 64 bits wide were.

With current 64- bit processors such as the based on the Core microarchitecture, the 128 -bit wide SSE registers are actually processed in one step. Even processors, the number of SSE registers increased to 16 in these 64- bit, referred similarly to the previous naming scheme as XMM8 to XMM15.

Support in the CPUs

Since SSE was one of the first SIMD extensions to the x86 architecture, and came on the market in 1999, have virtually all x86 CPUs in recent years SSE (as of 2013).

For example, supported AMD Athlon from a part of the present in the SSE instruction set commands (including those that work with 64 -bit registers). Here we also speak of an extension of MMX. Since the Athlon XP processor SSE is fully supported, so largely the result that even the own extension 3Dnow was abandoned.

Below is an overview from which CPU family the respective manufacturers have integrated SSE:

  • AMD: Athlon XP completely, the Athlon and Duron ( Morgan core processor since ) only partially.
  • Centaur Technology: at C3 Nehemiah processor core
  • Intel: Pentium III, Celeron with processor core Coppermine
  • Transmeta: from Efficeon