SuperSPARC

The Super Sparc is designed by Sun Microsystems superscalar microprocessor. Since Sun but did not have the appropriate manufacturing facilities, the processors were manufactured in the halls of Texas Instruments.

The first processors code-named Viking were announced in 1991, however, the delivery of the first SPARCstation 10 only began in May 1992. During the year 1994, the slightly improved successors Super Sparc II was presented.

  • 4.1 Literature

History

After the platform change for Sun -4 series was launched in 1987, began shortly after the development of a multiprocessor- capable successor of the current SPARC V7 generation. The aim was to develop a modern superscalar processor operating on the application, the most effective analysis of the Sun with three instructions per cycle, and has a built-in cache the most effective pipeline. In addition to the points already mentioned, offered this processor concept, compared to its predecessor, as well as an integrated floating point unit and the connection of an optional cache controller. This in turn should have the opportunity to address a large L2 cache. The start of production should take place as early as 1990, but has been repeatedly delayed due to difficulties in manufacturing.

During the MicroSPARC at Sun segment for Uniprozessorsysteme served, the Super Sparc was used according to its development as a multi- processor for workstations and supercomputers. The majority of the built processors was used in the SPARCstation 10/20 and in manufactured by others replicas. Also worth mentioning is the use in the most powerful servers Sun Sparc Center 2000, Cray CS6400 and Thinking Machines CM -5E, each with up to 20, 64, and 128 processors.

As the successor of the Super Sparc 1994 the UltraSPARC should take, however, the delivery of the first machines to winter 1995 was delayed. The resulting gap could not fill the Super Sparc, as he bent at 85 MHz to overheating in some machines and therefore the operation only in specific servers was admitted. To continue to compete with other systems, the HyperSparc was offered, which had until then been positioned as a super Sparc competitor on this platform.

Architecture

The microprocessor is based on the specifications of the SPARC V8 processor architecture and therefore inherits all the properties. The basic structure is a three- superscalar 32-bit processor core with two integer units ( IU ) and a floating point unit (FPU). The integer units feature a 4- stage pipeline and allow the Super Sparc perform up to two integer operations per clock. This high throughput is rarely achieved in real situations because of program branches and data dependencies. However, in order to increase the maximum efficiency, the branch prediction techniques, and data forwarding are implemented in the processor.

The floating point unit consists of two independent pipelines, one floating-point adder ( FADDER ) for addition, subtraction and logical operations, a floating point multiplier ( MULTIPLIER ) for multiplication and one floating point controller. Each of the two processing units is associated with one of the pipelines and is filled with data, if necessary. The Floating Point Controller removes all floating-point instructions from the last Piplelinestufe the IU, decides on the basis of type of instruction which Ausführunseinheit is responsible for the instruction and fill in the appropriate pipeline.

Like any SPARC has the Super sparc with a large register array of 128 integer and floating-point registers 32, which can be accessed directly, but only via the appropriate tab window. In addition there are eight global registers.

The Super Sparc II improved some aspects of the design. Thus, the floating point unit received another unit, the Floating Point Divide / Square Root (FDS ) for division and square root calculations, and thus a third pipeline. In addition, the integer register box has been redesigned to be easier to increase the clock rate.

Models

Super Sparc (Viking)

  • L1 cache: 20 KB ( data) 16 KB ( instructions )
  • L2 cache: no, 1 MB or 2 MB
  • SPARC V8
  • MBus / XBus
  • Release Date: 1991
  • Manufacturing Technology: 0.8 micron BiCMOS
  • Number of transistors: 3.1 million
  • Clock rates: 33-60 MHz
  • Model Numbers SM20: 1 CPU, not L2 cache bus 33 MHz: 33 MHz
  • SM21: 1 CPU, 1 MB L2 cache, 33 MHz Bus: 33 MHz
  • SM30: 1 CPU, no L2 cache, 36 MHz Bus: 36 MHz
  • SM40: 1 CPU, no L2 cache, 40 MHz Bus: 40 MHz
  • SM41: 1 CPU, 1 MB L2 cache, 40 MHz Bus: 40 MHz
  • SM50: 1 CPU, not L2 cache bus 50 MHz 50 MHz
  • SM51: 1 CPU, 1 MB L2 cache, 50 MHz Bus: 40 MHz
  • SM51 -2: 1 CPU, 2 MB L2 cache, 50 MHz Bus: 40 MHz
  • SM52: 2 CPU, 1 MB L2 cache, 45 MHz Bus: 40 MHz
  • SM52X: 2 CPU, 1 MB L2 cache, 50 MHz Bus: 40 MHz
  • SM61: 1 CPU, 1 MB L2 cache, 60 MHz Bus: 50 MHz
  • SM61 -2: 1 CPU, 2 MB L2 cache, 60 MHz Bus: 50 MHz

Super Sparc II ( Voyager )

  • L1 cache: 20 KB ( data) 16 KB ( instructions )
  • L2 cache: 1 MB or 2 MB
  • SPARC V8
  • MBus / XBus
  • Release Date: 1994
  • Manufacturing Technology: 0.8 micron BiCMOS
  • Number of transistors: 3.1 million
  • Clock rates: 75-90 MHz
  • Model Numbers SM71: 1 CPU, 1 MB L2 cache, 75 MHz Bus: 50 MHz
  • SM81: 1 CPU, 1 MB L2 cache, 85 MHz Bus: 50 MHz
  • SM81 -2: 1 CPU, 2 MB L2 cache, 85 MHz Bus: 50 MHz
  • SM91 -2: 1 CPU, 2 MB L2 cache, 90 MHz Bus: 50 MHz

Swell

Sun-4 Cache (computing) Connection Machine Floating-point unit Register window MBus (SPARC)
755326
de